Difficult in probing through chipscope

Hello Guys, I am finding difficult in probing virtex 2pro using chipscope. I am using chipscope pro logic inserter. I have following doubts regarding it

  1. In my top module (also netlist)i have any IP core which i have integrated and its black box IP(EDF netlist).I cannot see the black box IP in the TOP module in chipscope but its present in TOP module Netlist. I can view all the module except the netlist module . So i am not able to connect the signal of EDF IP to trigger signal. Why is it so??
  2. Can i not connect the IO port signal of TOP module to triggering signal of chipscope?. When i connected it gives error in implementation saying multiple drive. Is any other way to view the IO port signal along with the internal signal.

Thanks and regards, Williams

Reply to
stud_lang_jap
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can some one guide me setting ucf for DLLs.I am using clkx2,clkx4,clkx8.The board I am suing is spartan 2 FPGA,Xc2s200 PQ208.I got the below errors.

RROR:Place - Could not find an automatic placement for the following components: clock of type GCLK IOB is placed at GCLKPAD3 dll2x of type DLL is unplaced clk2xg of type GCLK BUFFER is unplaced dll4x of type DLL is unplaced clk4xg of type GCLK BUFFER is unplaced dll8x of type DLL is unplaced clk8xg of type GCLK BUFFER is unplaced Xilinx requires using locate constraints to preplace such connected GCLK/GCLKIO/DLL components.

Reply to
sri

Which version of ChipScope Pro are you using? Version 7.1i added the ability to Insert probes within any portion of a design regardless of the type and number of netlists used. In other words, all EDIF or NGC files are assembled before the Inserter is opened, so any design flow (Modular Design, IP cores, design core resuse, etc) is supported. Any encrypted IP cores will still remain hidden for security reasons.

If you are using ChipScope versions prior to 7.1i, this can still be done, albeit manually. Simply run NGCBUILD on your top level netlist before opening the Inserter, as documented in Solution #20185

You are not permitted to connect ChipScope probes to IO ports, as the logic required for the probes are built with general logic and must be connected to internal nodes. Connect your probes to the internal sides of IO buffers to get the same data. For example, if you are using XST, connect your probe to MYPORT_IBUF instead of MYPORT, etc.

thanks, David Dye Xilinx Colorado

Reply to
David Dye

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