Differential timing specification in Xilinx FPGA

Hello,

I am searching how to specify a relative timing constraint (and not a placement constraint) that would be enforced either by the VHDL synthesis tool or the place and route tool in the following case (decoding of a serial link data/strobe like the one depicted in figure 5 of

formatting link

) :

the serial link is made of one data line D and one strobe line S

the clock CLK at half bit rate is regenerated by an XOR between D and S

the data signal D is sampled on both the rising edge and the falling edge of CLK.

The problem is that when the clock edge is caused by a change on the D line, the setup time is very dependant on the routing of D, S and CLK. Manual placement constraints allow to solve the problem, but it is rather tricky. I would prefer to find a way to specify a relative timing contraint between D and CLK.

Marc

Hello, My first message was probably too specific : I would like to know whether it is possible to specify explicitely either at the level of the synthesizable VHDL model, or as a place & route constraint a timing constraint ensuring a correct setup time at the input of a flip-flop, when the clock of the flip flop is a combinatorial expression of its data input and of another signal (XOR). This other signal never change at a time where it may cause setup or hold violation. The target is a Virtex 2 FPGA, VHDL syntesis : Synplify pro, P&R : Xilinx ISE 6.2 The only way I found to ensure the setup time is to add a Xilinx BUFG buffer to delay the combinatorial expression w.r.t the data, or to force the placement of the combinatorial expression and of the flip flop. Is it possible to do it more cleanly ? Marc

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