Dear All, I'll phrase my questions differently from my last attempt!
Q1. If I instantiate a 2.5V LVDS input with differential termination in my design, e.g. LVDS_25_DT, then I power its VCCO with 3.3V, what happens? I think the input DC thresholds should stay the same, as they're powered from VCCAUX, but what about the termination impedance? Q2. If I instantiate a 2.5V LVDS output in my design, then I power its VCCO with 3.3V, what happens? What are the output's DC characteristics? Q3. Will Xilinx publish pictures of the various outputs so I can figure this out myself? You know, those little diagrams with transistors, current sources and stuff that a lot of other datasheets have!
You exceed the abs max specs, and you void any warranties or guarantees.
What are the output's DC characteristics?
The schematics for the IOBs are so large that they crash spice simulators. So, no, we are not going to publish any schematics, other than the simplified ones that are already in the datasheet and user guides.
Hi Austin, Thanks for that, very much appreciated, I knew you'd be able to help! So, I've added some more questions! thanks again, Syms.
p.s. Please don't think I'm ungrateful, I'm a big fan of what you guys have done with the IOs! The on-chip termination is a BIG help, as is the excellent wide common mode range of the diff inputs!
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OK, cool! But why does it say in tiny writing in "Figure 22: LVDS Differential Termination Usage Examples" from "DS083-2 (v2.8) September 10,
2003", the Virtex-II Pro functional description:- "NOTE: Only 2.5V LVDS standards are supported (VCCO = 2.5V only)" ? Will the latest software prevent me from combining LVDS_25_DT and LVCMOS33 in the same bank? It says in answer 17244:- "Requirement to Turn on the On-chip Input Differential Termination The VCCO of the I/O bank must be connected to 2.5V to provide 100 ohms of effective termination. NOTE: Starting ISE 6.1i, this requirement is implemented in the software. " Are there any work-arounds? Like use LVCMOS25s and then power VCCO @ 3.3V?
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I couldn't be sure I'd found this specification. I found "Table 8: LVDS DC Specifications" in DS083-3 where there is a max for VCCO, but it's not clear to me whether this is an abs max spec, or a spec for VCCO to meet the other DC specs in the table. Could you clarify for me? I presume 3.3V won't break the LVDS circuitry as it's probably still powered from VCCO when LVCMOS33, for example, is used in the IOB. Correct?
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