Differential pairs per Bank

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
Hello,

we want to use a Spartan-3A to collect signals of about 100
differential lines. This type offers the possibility for on-chip LVDS
termination. Is there a limit how many pairs per bank can be
terminated via the on-chip resistor? Where may I find further
information?

Thanks Tom


Re: Differential pairs per Bank
Quoted text here. Click to load it
I'm not really fluent in the Spartan-3A-architecture, but if it's
anything like Virtex, then there should be no limit. The only
restriction is that for some I/O-pins in a bank, there is no second pin
for the differential pair, i.e. some pins can only be used single-ended.
So the overall total of differential pairs you can use in the FPGA does
not equal the total number of IOs/2.

But in Spartan-3A, your VCCO needs to be 3.3V if you want the internal
terminations to be 100R (see page 339 of ug331 from Dec 5, 2006).
Strange enough, in Spartan-3E, Virtex-II Pro and Virtex-4, VCCO needs to
be 2.5V for the correct termination value, so this is something one has
to look out for.

As I found out after installing on Friday, ISE9.1 stops the place and
route with an error message if you don't watch out for this. In earlier
versions of the tools, this did not even produce a warning.

--
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...

Re: Differential pairs per Bank
Quoted text here. Click to load it


Often LVDS on-chip Termination is a  power hog  on Xilinx chips.
Consider using a multi channel LVDS transceiver. like the SN65LVDM1677. It
eases layout and spares you a lot of pins.

--
Uwe Bonnes                 snipped-for-privacy@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
We've slightly trimmed the long signature. Click to see the full one.
Re: Differential pairs per Bank
Quoted text here. Click to load it
Hi Uwe,
Are you saying that LVDS uses more power than LVDS_DT from the Xilinx
supplies? That surprises me. Could you point me in the direction of some
documentation for this? Or maybe you're refering to the DCI modes?
Thanks, Syms.



Re: Differential pairs per Bank
Quoted text here. Click to load it

I meant the problem with excessive power for LVDS with on-chip DCI
termination.
--
Uwe Bonnes                 snipped-for-privacy@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
We've slightly trimmed the long signature. Click to see the full one.
Re: Differential pairs per Bank
Quoted text here. Click to load it

Be careful also that you do not fry the Spartan 3A when you use DCI
termination for 100 differential lines as all the power dissipated will
be within the chip. The advantage of using external termination
resistors or LVDS devices is that the power is not dissipated within the
FPGA.


Ben

Re: Differential pairs per Bank
Quoted text here. Click to load it

Only the Spartan-3 offers DCI - not Spartan-3A, not even Spartan-3E.
The DIFF_TERM is offered in the 3A and 3E but DCI is expected for the
Spartan-3 base family only.  Starting with the Virtex-2Pro (it appears,
from an Austin Lesea response back in early 2004) the LVDS_DT uses "a
true differential termination (a resistor) that is switched in
between + and - inputs" which shouldn't take up *any* significant power.

http://groups.google.com/group/comp.arch.fpga/msg/c0e735c3ecf07621 ?

Re: Differential pairs per Bank
Why speculate when it is all described in the appropriate user guide?
The differential termination is internal, and consumes hardly any
power, since it is truly differential, not the fake differential power
hog implemented in DCI.
And UG331 on page 338/339 clearly states that you can use either 3.3
or 2.5 V (but at 2.5 V the differential termination resistor is not as
precise a value).

Peter Alfke
==========================
On Jan 30, 12:14 pm, Uwe Bonnes < snipped-for-privacy@hertz.ikp.physik.tu-
darmstadt.de> wrote:
Quoted text here. Click to load it



Site Timeline