Hello,
we want to use a Spartan-3A to collect signals of about 100 differential lines. This type offers the possibility for on-chip LVDS termination. Is there a limit how many pairs per bank can be terminated via the on-chip resistor? Where may I find further information?
Thanks Tom
I'm not really fluent in the Spartan-3A-architecture, but if it's anything like Virtex, then there should be no limit. The only restriction is that for some I/O-pins in a bank, there is no second pin for the differential pair, i.e. some pins can only be used single-ended. So the overall total of differential pairs you can use in the FPGA does not equal the total number of IOs/2.
But in Spartan-3A, your VCCO needs to be 3.3V if you want the internal terminations to be 100R (see page 339 of ug331 from Dec 5, 2006). Strange enough, in Spartan-3E, Virtex-II Pro and Virtex-4, VCCO needs to be 2.5V for the correct termination value, so this is something one has to look out for.
As I found out after installing on Friday, ISE9.1 stops the place and route with an error message if you don't watch out for this. In earlier versions of the tools, this did not even produce a warning.
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Often LVDS on-chip Termination is a power hog on Xilinx chips. Consider using a multi channel LVDS transceiver. like the SN65LVDM1677. It eases layout and spares you a lot of pins.
-- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Hi Uwe, Are you saying that LVDS uses more power than LVDS_DT from the Xilinx supplies? That surprises me. Could you point me in the direction of some documentation for this? Or maybe you're refering to the DCI modes? Thanks, Syms.
I meant the problem with excessive power for LVDS with on-chip DCI termination.
-- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Be careful also that you do not fry the Spartan 3A when you use DCI termination for 100 differential lines as all the power dissipated will be within the chip. The advantage of using external termination resistors or LVDS devices is that the power is not dissipated within the FPGA.
Ben
Only the Spartan-3 offers DCI - not Spartan-3A, not even Spartan-3E. The DIFF_TERM is offered in the 3A and 3E but DCI is expected for the Spartan-3 base family only. Starting with the Virtex-2Pro (it appears, from an Austin Lesea response back in early 2004) the LVDS_DT uses "a true differential termination (a resistor) that is switched in between + and - inputs" which shouldn't take up *any* significant power.
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