Differential output drive-strength in spartan-3

I am instantiating an LVPECL iobuffer in a xilinx spartan-3 device. This buffer is sending out data at 150Mbps into an LVPECL receiver chip located about 18 inches away. The sent signal doesn't have enough amplitude to overcome the hysteresis in the receiver. My measurements indicate that there is very little attenuation in this signal from driver to receiver. Its just that the signal at the fpga is of almost no amplitude. If i lower the clock rate to 100Mbps it works fine. I don't really care about standards compliance here, i just want it to work ( at 150Mbps). Is there some way i can increase the slew rate or drive strength of the driver? Perhaps changing io-standards?

Thanks in advance,

Jon Pry

Reply to
jonpry
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Jon,

Using the two external series 70 ohm, and external 240 ohm then over a

100 ohm (or two 50 ohm) t-line, terminated in 100 ohms (and another Spartan 3 set of inputs), I get ~ 1700 mV p-p at 150 MHz in my Hyperlynx simulations.

Are you sure you have the required external networks properly wired?

Have you driven the + output and - outputs out of phase? (one goes hi, while the other goes lo...).

formatting link

Figure 32, page 65 of 126.

Austin

Reply to
austin

This is the verilog code i use to instantiate the driver

defparam laser_buf.IOSTANDARD = "LVPECL_25";

OBUFDS laser_buf (.I(laser), .O(laser_p), .OB(laser_n) );

It is then loc'd to a pin in the ucf file. afaik, OBUFDS always drives the pins out of phase. i verified this on a scope, and it works fine at lower speed. i have the 70 ohm resistors, but not the 240 as i think it is just there to lower the voltage to be within the lvpecl spec, which i don't care about.

i suspect that setting IO_STANDARD=LVPECL does some things in the background, like set the drive strength and slew rate as low as possible.

this output need not be relative to any clock, so maybe the best thing is to use 2 lvcmos buffers driven out of phase.

Reply to
jonpry

Jon,

OK, that all should work just fine. As low as 4mA fast LVCMOS is what is used for LVPECL, and is plenty fast for a clean 6.6ns "eye" pattern even at the slow/weak IBIS corner.

The fact that it works at 100 MHz, and does not at 150 MHz does not match the simulation AT ALL! From this, I suspect there is something else going on (capacitive loading, inductive t-line, asymmetric/bad duty cycle, ... etc.) which causes the "wheels to fall off" at 150 MHz!

If you change your programming for two separate out of phase drivers to two 4 mA FAST LVCMOS, there should be no change from the LVPECL case you have now.

If there is, then the IO standard isn't setting the bits right in the configuration, and that would be a software bug in bitgen (but, I can't imagine it working at 100 MHz, and then not at 150 MHz!!!).

Boosting the drive strength won't do anything at all.

Leaving out the 240 ohms may be the cause of your problem, as the transmit is also matched to 100 ohms (if the reflection is just right, you could be canceling your receive signal because of transmit impedance mis-match).

Austin

Reply to
austin

Apparently i am retarded and in one of the connectors the wires were off by one. So only one line of my diff pair was actually connected. There was so much coupling between the wires that on the scope it looked like they were both hooked up. It is rather amazing this worked at all. My guess is that there was enough capacitance in the termination resistor to cause a phase lag in the other wire. I didn't get around to trying the 240 ohm resistor. Sorry for troubling you and thanks for all the help.

Reply to
jonpry

Jon,

No need to apologize!

Congratulations: you FOUND IT!

That makes you smarter than 99.9995% of the rest of us in our 'armchairs'!

Austin

Reply to
austin

Interestingly, it's possible to get this wrong even with the cable wired correctly (and no tracking mistake at either end).

Recently, I saw a 20-way cable where each end had the same type of connector and a multimeter confirmed this wiring:

A01---B20 A02---B19 A03---B18 : : : A19---B02 A20---B01

My first thought was "this cable is symmetrical - it doesn't matter which way round I connect it".

But it turned out that (for example):

the wiring from A08/A09 to B13/B12 is a twisted pair the wiring from B08/B09 to A13/A12 is not

So, the cable was reversible mechanically and for DC, but not for AC.

One connector had a cryptic label which just read BOARD. Maybe the designer should have used two different connectors (or arranged the twisted pairs symmetrically). I hope he isn't designing cables for use in aircraft.

Mike

Reply to
MikeShepherd564

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