Hi all,
I'm doing a project on a Virtex-2P-40. The FPGA is fed with a differential clock pair and I am not quite sure how to tell EDK that this is the case. I have tried to use a small custom made core to connect the two clock inputs (pins H18 and J18) to an IBUFGDS primitive, but that is not understood by the synthesis which connects the inputs to two different BUFGP primitives prior to my small IBUF-core. In my oppinion the clock should be connected to a IBUFGDS and the output from the buffer should be connected to the DCM.
I'm feeling clueless, and would sure appreciate any input on this matter leading me in the right direction.
Regards