Different synthesis report between ISE-xst and EDK-xst

Hi all!

I've really trouble to implement a simple application on a XUP Virtex- II Board using the PPC and PLB as Interface. I simply want to pass two inputs into the logic-core wire them to two output ports. Additionally there shall be two output ports one driven by slvreg0(0) and the other by slvreg1(0). To implement that I used the created template from the "Create and Import Wizard" for an PLB interface.

The Problem is after synthesising the system in EDK9.1 my PPC won't run at all. I simply tried to print an "Entering main" by using the uart in my c- code. I didn't interacted with my core. But it didn't run.

After that I had a look in the schematic report of ISE 9.1. For that I used the ISE Projekt created by the "Create and Import Peripheral Wizard". The first thing I found was that there was a different chip selected than I use in EDK9.1. The second point was that the synthesis report in ISE diverted from thta generated in EDK.

Has anyone discovered the same problem, or does anyone now wether ISE- xst and EDK-xst use different parameters. How can I be sure, that the schematic that is presented is the same that EDK would produce???

The other thing I found out by having a lokk at the schematic is that the Port "Us_port_one_toggel_out" was replaced by the entire 32Bit vector slvreg0.

I hope that one of you guys cann help me out at this point.

Best regards

Sven

Here is an example of my user_logic.vhd:

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SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is begin

if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Reset = '1' then slv_reg0 '0'); slv_reg1 '0'); slv_reg2 '0'); slv_reg3 '0'); else case slv_reg_write_select is when "1000" =>

for byte_index in 0 to (C_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg0(byte_index*8 to byte_index*8+7) for byte_index in 0 to (C_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg1(byte_index*8 to byte_index*8+7) for byte_index in 0 to (C_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg2(byte_index*8 to byte_index*8+7) for byte_index in 0 to (C_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg3(byte_index*8 to byte_index*8+7) null; end case; end if; end if;

end process SLAVE_REG_WRITE_PROC;

--SA Us_int_one_out

Reply to
SvenA
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I think I found the problem for the not running c-code. After I generated a new linker script the c-code ran. The core is working as well. I drove a 1Khz signal trough my to wired in- and outputs. It looks like I missunderstood the RTL-Schematic from ISE.

But there is still the Question whether ISE and EDK run XSt with different parameters and why?

Regards

Sven

Reply to
SvenA

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