different I/O buffers available inXilinx FPGA

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could anyone please explain me the difference between the buffers IBUF
OBUF BUFGP BUFGDLL BUFT etc available in XILINX FPGA.


Re: different I/O buffers available inXilinx FPGA
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RTFM

antti



Re: different I/O buffers available inXilinx FPGA
Hi Antti Lukats,

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Are you having a bad day?

Ben

Re: different I/O buffers available inXilinx FPGA
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YES.
I wanted actually to appologizy to the OP, as my comment wasnt justified.
Sorry.

Antti
PS Ben, I will reply to you separatly.



Re: different I/O buffers available inXilinx FPGA

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IBUF

Just have a look at
  <Xilinx-Install-Dir>\doc\usenglish\books\docs\lib\lib.pdf

Jochen


Re: different I/O buffers available inXilinx FPGA

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or...
http://toolbox.xilinx.com/docsan/xilinx6/books/docs/lib/lib.pdf

EG

Re: different I/O buffers available inXilinx FPGA
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I like this one best:

http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0027_11.html

or this for Virtex-4:

http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/v4lsc/v4lsc0013_4.html

cu,
Sean

Re: different I/O buffers available inXilinx FPGA
thanks a lottt


Re: different I/O buffers available inXilinx FPGA
As others have pointed out, the manual does explain them.  However,
maybe more of what you are looking for is when to use them.  This is all
off the top of my head.  My apologies for any minor inaccuracies.

IBUF is the normal input buffer that connects an IOB from an input pin
to the internal FPGA logic.

IBUFG is the global input buffer.  It is for the same purpose as IBUF
except one uses it where one is connecting to a DCM or a BUFGMUX.  This
minimizes the skew of signals coming from off chip.  For example, if
your crystal is used by the FPGA and other devices on the board one
would want the clock inside the FPGA to be as close to the clock outside
the FPGA so that in the end your outputs of the FPGA are as close to the
same clock edge as possible.  If one is using clock feedback from the
board IBUFG should also be used.

OBUF is the opposite of the IBUF, connecting internal logic to an IOB
for output.

BUFG is one use of a BUFGMUX (see the appropriate FPGA user guide) and
is used to distribute a signal inside the FPGA using the global nets to
minimize skew inside the FPGA.  BUFGs are generally used for clocks,
resets, and signals where minimal skew is very important.  If one is
using a DCM and the output goes to more than one location, one probably
should use a BUFG.

BUFGP is a IBUFG followed by a BUFG.  A BUFGP is used when one wants to
distribute a signal across the FPGA with minimal skew and one is not
using a DCM to do it.

BUFGDLL is an IBUFG driving a CLKDLL.  The CLKDLL is the primitives in
Spartan II, Spartan IIe, Virtex, and Virtex-e prior to the DCM.

BUFT is a tri-state buffer.  This is used when one needs to implement
tri-state.

There are other buffers too, like IOBUF for bi-directional and xBUFDS
for differential.

If you let them, the ISE tools will take care of a lot of this buffering
for you.  Some thing like tri-state need to be taken care of by the
user.  EDK takes care of its own buffers if it is a top-level design and
otherwise provides a stub to the user.

This post is my own opinion, and not an official Xilinx post.  Reverse
domain and remove the NOSPAM from e-mail address to respond by e-mail.

vlsi_learner wrote:

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Re: different I/O buffers available inXilinx FPGA
thanks Benjamin.. i got the idea...this was what i was looking for


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