Difference in output between testbench and chipscope

Hi Subhasri,

are the fifo write data generated internally or are they external data ?

Rgds Andr=E9

Hi, The fifo write data is generated internally.

module FifoTest(clk, data_out, d_in);

input clk; output [7:0] data_out; output [7:0] d_in;

wire wr_en; wire rd_en; wire [7:0] d_in; wire [7:0] data_out; reg rd_en_reg; reg [7:0] data_in_reg;

//Wires tied to values wire reset =3D 1'b0; assign wr_en =3D (reset) ? 1'b0 : 1'b1; assign rd_en =3D rd_en_reg;

// The following must be inserted into your Verilog file for this // core to be instantiated. Change the instance name and port connections // (in parentheses) to your own signal names.

fifo_8bit_32deep Sync_Fifo ( .clk(clk), .sinit(reset), .din(d_in), .wr_en(wr_en), .rd_en(rd_en), .dout(data_out) );

//Generate Data assign d_in =3D data_in_reg; always @ (posedge clk) if(reset) data_in_reg

fifo_8bit_32deep Sync_Fifo (

You connect d_in to the input of the FIFO and at the same time you define it as OUTPUT of your whole module ?

Rgds Andr=E9