Hi all,
I've something strange in my design... I think there is something I don't understand..
I've a clock distributed on a global clock network, It seems to be ok.. In the "Clock report" from the ISE PAR, I can read a "net skew" of
0.276ns and a max delay of 1.779ns (I'm using a virtex5 XC5VLX50). But when I use trce to look for timing violations, I found hold violations With a "data path delay" of 2.476, and my "max delay" for the clock ( 1.779ns ), it should work.. But trce reports a "positive clock path skew" equal to 6.898ns.. that's why I've some timing violations...My question is, how can I've a "positive clock path skew" greater than the "max delay" from the clock report ? Is it a consequence of the clock fanout (374 ) ? Is it because my clock is used in different clock regions ?
Thanks for your answers,
Best Regards, Michel.