Following up on John Providenza's question about the DIFF_OUT buffer feature, I've put together a small example which builds a complementary clock input buffer out of two normal IBUFGDS's.
Also for reference, I've copied my original notes about this handy feature of the V2 & S3 families.
Brian
All the V2-ish differential input buffers have a complementary output available, that can be used to create a 180 degree clock without needing a DCM.
These can also be used just to invert a differential input without needing any other logic (or board cuts & jumps).
Look at the DIFFS component in fpga_editor to see what's going on; besides the normal 'phantom' route from the DIFFS to the DIFFM, there's also a route from the DIFFM to a differential receiver in the DIFFS that outputs the complement signal.
I first spotted these when they showed up in early versions of XAPP622 as a hard macro.
Support & tool bugs for these have varied version to version, see Answer Record 21958 for recent problems.
I've banged into various other problems in using them over the years; if I get a chance this weekend, I'll try to dig up some old webcase code showing how to create one out of two normal IBUF{G}DS's as a work around.
These can be used on regular IOB inputs as well as global clock inputs, but you've generally needed to LOC the global input buffer and bufg's to allowed sites to get this to work.
search for ibufgds_diff_out ibufds_diff_out
--
--
-- diff_out buffer example
--
-- shows how to create complementary internal clocks using
-- IBUF{G}DS's with neither a DCM nor local inversion required
--
-- forwards a global clock input to output, output/2
--
-- substitutes two ibuf{g}ds's for ibuf{g}ds_diff_out component;
-- various tool revs have choked when using attributes on those
--
-- intended for V2-ish family members
--
-- !!! example LOC constraints specific to XC3S200-FG256 !!!
--
-- COMPLETELY UNTESTED; SYNTHESIZED WITH 6.3 & EXAMINED IN FPGA_EDITOR
--
-- Input Clocking:
-- this example doesn't use the resulting clock for DDR inputs,
-- but best (or at least easier to analyze) DDR input timing may
-- result when using CLB registers rather than DDR IOB input regs