I was watching Avnets' sponcered video with Robert Pease and Howard Johnson where National had a board with a ADC08D1500 dual ADC tied directly into a Virtex 4. The videos, datasheets, etc may be found at:
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The LVDS clock coming from the ADC is 750MHz. They route this clock directly to the Virtex 4. When I look at the specs. for the Virtex 4, this would seem to be way outside of what it is rated for.
My question is this, did National do some neat trick to make this work, or did they just exceed the specs of the device knowing it was not a production unit and did not really worry about it? Or did I miss something?
Also, if anyone purchased the eval. board, I would be interested in hearing if U5 was populated with the LMH6550 or some other part.
While it is true that we don't specify a LVDS clock that high in frequency, the IO is perfectly capable of going way past 1.2GHz, so it becomes a question of duty cycle distortion on the clock resources inside.
It won't be 45/55% like the spec sheet says, but it will still have a perfectly good pulse there. Obviously National is using this. Since they are using it, that makes Xilinx kind of responsible for some support of this application. What that means is that if you use it the way they did, we will support it (wiring, t-lines, terminations, paths used, speed grade, etc.).
Similar to the PCI interface, the basic PCI operates outside of our specifications, but we support it, as we have tested our PCI core in our parts, and found it to work just fine.
This is known as support of "application outside of specification." If you are curious, there are very few of these. PCI is the largest. After that, I would guess you fall into something like the National application (very small compared with the overall usage).
Aust> I was watching Avnets' sponcered video with Robert Pease and Howard
The National A/D's have an on-board 1:2 demux, so at a clock rate of 1.5 Ghz, the 8 bit samples come out 16 bits wide with the DCLK output clock selectable as either SDR (750 Mhz) or DDR (375 MHz).
No out of spec handwaving dispensations are required from San Jose.
Brian
p.s. Re your other post, the new high-end LatticeSC parts are claiming 2Gbps parallel LVDS I/O, with some interesting split-to-VTT and center-tap-cap on-chip termination modes.
I agree with what you wrote, however the video actually shows the
750MHz LVDS output and they talk about it running at this speed. So, I assume that they are running SDR with DES. Did you watch the video, or do you have some insider information on the project?
I think I wrote DES in that last note, which would have been incorrect.
Austin,
Thanks for the input. Do you know if the parts are indeed running at the 750MHz as stated in the video? Talking with Altera they also claim the part was running in DDR mode, again not what the video shows. I have tried to contact National about the design, but no luck yet.
"It won't be 45/55% like the spec sheet says, but it will still have a perfectly good pulse there. Obviously National is using this. Since they are using it, that makes Xilinx kind of responsible for some support of this application. "
I am not sure what the arrangement would be that Xilinx would be responsible for what I would consider a bad design (assuming they really are running the part at 750MHz). If Xilinx does plan to support higher clock rates, what does this mean to me as a designer? Are there any application notes that talk about overclocking the Virtex 4?
Just an FYI, if I try to do this same thing with the Stratix II and Quartus, the tool will spit out an error. I spoke with Altera about this and they made the comment that they do not allow the parts to be over driven.
I watched the video, but offhand, I don't recall them actually showing the clock the to FPGA at 750 MHz, other than at the viewgraph level- which segment of the video is that 750 MHz reference in?
If you look at Nationals app note:
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Page 7 shows the 1/4 Fs clock being used to clock the FPGA at Fs=1GHz, Fddr=250 MHz
As if the FPGA Police will swoop down on you and have you arrested.
Right.
In the fine tradition of:
1) knowing that all components are designed to meet certain specifications
2) and that most of the elements of a design normally exceed the specifications
3) and that it may be that you are willing to sacrifice one specification over another (max frequency vs duty cycle)
engineers for decades have used components "outside" of their stated specifications.
The 'penalty' for being caught, is that the manufacturer may state that the usage is not covered by the specifications, and thus, not guaranteed.
Since the guarantee is just one of "take that part out, and replace it with another" the clever engineer has been taking advantage of their components for many years.
Of course, the clever engineer has to perform a complete verification and characterization on their own to be sure that suddenly the feature that they are using doesn't go away. For example: is the usage one that has wide margin, or is it very tight? How does the usage vary with voltage and temperature? Have you tested it on devices from different lots? Did you call or ask someone at the factory what their opinion was?
A very common practice is to buy commercial grade components. and qualify them yourself for an application that is not commercial grade.
Maybe you just need to go from -20C to +85C, and you know, as a reasonably intelligent engineer, that the I grade and C grade parts are pretty similar silicon, and all most of the difference is the test program. Since getting colder is usually not a problem with timing, or performance (at least is used to be, can't say that is true any longer), it is a safe bet to say that a C grade part will work fine at -20C?
Now the previous practice was pretty common, and I am not sure of how common that still is.
Getting back to the clock.
How fast do you want to go? What duty cycle distortion can you tolerate? Over what temperature range? How many do you need to make? Does it still meet the thermal Tj requirements? If it is found "to work" at room temp, and nominal voltages, looks like there is a lot more engineering that you have to do.
I have no idea what National did (haven't seen the presentation). I am sure it is all there in the documentation, as it has been pointed out. And, it sounds like they have a clock/4 option, which is just smart.
That is always a good idea, but the best way to keep customers out of trouble is to educate them. Providing mindless rules without a good reason can just lead to more headaches.
The conversation from Xilinx would go like this: "Do you use the part within its specifications?" Your answer - 'No...' "OK, so what was your expectation?" 'that it would work' "And does it, in fact work?" 'well, not always' "Well, I'm really sorry about that, maybe there is some way to work around this issue, and get it to work within specifications and do what you want. Let me understand your application..."
Basically, Xilinx is not going to throw you to the wolves. But we are not going to redesign the chip for you, either.
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Figure 4, DDR clocking shows how a 1.5 GHz clock into the ADC, comes out as a clock/4 on each of the 0 and 90 degree clocks, so that you can capture four 8 bit bytes in the clock/4 period, (using both rising and falling edges of the 0 and 90 degree data clocks outs). So it looks to me like no "laws" are broken....
Depends on who "we" are. If you buy $10K of Xilinx parts per year, I expect they're not going to go as far out of their way to support you as if you buy $10M per year. Like any other business, Xilinx has finite resources available to support customers, and has to devote them in such a way as to maximize return. That's part of their fiduciary responsibility to their shareholders.
If a small customer wants to deliberately use a part outside its specs, the answer is probably "you're on your own", but if i vary big customer wants it, they can probably get Xilinx to have engineering resources assigned to validating and/or qualifying the part at the desired specs.
That said, in my experience Xilinx does a very good job of supporting small customers, within the limits of what can reasonably be expected.
Thanks for the detailed timeline; although the clock on the nearby slide is labeled '750 MHz LVDS', shortly after that "ah..", H.J. refers to the 750 MHz as an "output rate".
Also, there's a link on the video page to the Xcell article:
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which says: "For a 1.5 GHz sample rate, the conversion data will be output synchronous to a 750 MHz clock. Even at this reduced speed, FPGA memories and latches would not be able to accept this data directly. It is therefore beneficial to make use of a DDR method, where data is presented to the outputs on the both the rising and falling edges of the clock (Figure 4).
Although the data rate remains the same for DDR signaling, the clock frequency is halved again to a more manageable 375 MHz"
Talking with National, they stated that when running the Virtex 4 at
750MHz that they saw about a 20 deg. C rise. Other than this they saw no problems. They saw no reason to run the part in this mode and switched. It sounds like the board still supports both modes. I guess the video was right, but they had a change in heart.
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