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DFS to generate Frequencies slightly apart

Hello,

for some legacy instrument, I need to replace AM796X Taxichips doing a

9B11B encoding/decoding. The Taxichip is long EOL, and replacement chips I know only do 8B10B or 10B 12B Data encoding can easily be done with BRAMs as ROM, and also the aligned receive data stream. For receiving, I plan to use the XAPP224 datarecovery. However having the data recovery run at the same nominal frequency like the transmitter, two bits can be received in one receiver clock cycle. This will make data alignment harder. Running the receiver clock a little bit higher, say 125 vs 125.1 MHz, the two bit receive situation can be avoided. The Xilinx DFS can "only" multiply by 2..32 and divide by 1..32. With a clock frequency of 20 MHz, I could run at transmitter at 125 MHZ and and the receiver at 130 MHz, imho too far apart.

Any idea how to generate frequencies slightly apart?

Thanks

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply to
Uwe Bonnes
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Hi Uwe,

But not much, are you man or mouse! ;-)

20 * 19 / 3 = 126.67

Seriously, go with the exact 125MHz Rx clock thing. The additional complexity will be worth it as you design will be a _lot_ more jitter tolerant. Think what happens as the data edges and the clock edges start to align. If there's jitter, the thing can flip back and forth between states. E.g., if these numbers represent the number of bits received:-

1,1,1,1,0,2,0,1,1,1,1

even though you really wanted:-

1,1,1,1,0,1,1,1,1,1,1

Cheers, Syms.

Reply to
Symon

...and another thing. If you use the Tx clock as your Rx sampling clock, it's trivial to pass data between the Rx and Tx clock domains. Well worth the extra logic. HTH, Syms.

Reply to
Symon

Uwe

Have you thought of using an analogue pll multiplier chip like a ICS8442. We use this chip in some unusual situations because it can run it's VCO to a very high frequency and for that matter can supply it to FPGA as a LVDS clock.

Once you have the clock can you then use phases of the clock to recover your data maybe even then using a DCM to phase shift if needed.

John Adair Enterpo> Hello,

Reply to
John Adair

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