hi to all: i have problem of drawing the state diagram could anyone please help me out thank alot:)
library IEEE; USE ieee.std_logic_1164.ALL; ENTITY dte IS PORT ( rst,dcr,ri,cd,cts,rxd,data,clk: in std_logic; dtr,start,rts,txd,out_dte: out std_logic); END dte; ARCHITECTURE dte_arch OF dte IS TYPE state IS (st0,st1,st2,st3,st4,st5,st6,st7,st8,st9, st10,st11,st12,st13,st14,st15,st16,st17,st18,st19, st20,st21,st22,st23,st24,st25,st26,st27,st28,st29); SIGNAL present_dte,next_dte:STATE; BEGIN processdte: PROCESS (rst,dcr,ri,cd,cts,rxd,data,clk) BEGIN if rst='0' then present_dte