Design report does not show BRAM usage

Read the synthesis report with care. It looks like the all the blockram and the surrounding circuits were removed because the output of the circuit is not used or the input is perhaps stable. Some typo in the instantiation may cause this.

Bye

Could someone please share a sample code which instantiates the BRAM blocks?

Thanks, Bhanu

Here I use one block as 8/32 Bit: /* * Tie unused data/address High (ug331, p.155 * Readout data is in upper portion */ RAMB16_S9_S36 ram1( .DOA(scaler_dout), .DOB(scaler_read_data), .DOPA(), .DOPB(), .ADDRA({{3{1'b1}},byteaddress[7:0]}), .ADDRB({{2{1'b1}},scaler_addr}), .CLKA(clk), .CLKB(clk), .DIA({8{1'b1}}), .DIB(scaler_write_data), .DIPA(4'b1), .DIPB(4'b1), .ENA((address == `SCALER)), .ENB(scaler_ena), .SSRA(1'b0), .SSRB(scaler_rst_cycle), .WEA(1'b0), .WEB(scaler_wea) );

The 8-bit side only reads the ram

This is what I have, please tell me if something seems wrong here.

RAMB16_S36_S36 CAC1 (.DOA (DOA_CAC1), .DOB (DOB_CAC1), .DOPA (DOPA_CAC1), .DOPB (DOPB_CAC1), .ADDRA (ADDRA_CAC1), .ADDRB (ADDRB_CAC1), .CLKA (Bus2IP_Clk), .CLKB (Bus2IP_Clk), .DIA (DIA_CAC1), .DIB (DIB_CAC1), .DIPA (DIPA_CAC1), .DIPB (DIPB_CAC1), .ENA (ENA_CAC1), .ENB (ENB_CAC1), .SSRA (1'b0), .SSRB (1'b0), .WEA (WEA_CAC1), .WEB (WEB_CAC1));

defparam CAC1.INIT_00 =

Thanks, Bhanu

Uwe B> Bhanu Chandra wrote:

This is what I have, please tell me if something seems wrong here since this is the code that does not make BRAM usage appear in the design report.

RAMB16_S36_S36 CAC1 (.DOA (DOA_CAC1), .DOB (DOB_CAC1), .DOPA (DOPA_CAC1), .DOPB (DOPB_CAC1), .ADDRA (ADDRA_CAC1), .ADDRB (ADDRB_CAC1), .CLKA (Bus2IP_Clk), .CLKB (Bus2IP_Clk), .DIA (DIA_CAC1), .DIB (DIB_CAC1), .DIPA (DIPA_CAC1), .DIPB (DIPB_CAC1), .ENA (ENA_CAC1), .ENB (ENB_CAC1), .SSRA (1'b0), .SSRB (1'b0), .WEA (WEA_CAC1), .WEB (WEB_CAC1));

defparam CAC1.INIT_00 =

Thanks, Bhanu

Uwe B> Bhanu Chandra wrote:

Seems like this is not the issue. What happened is that I had created a .h file within which I was doing all the instantiation. Possible that it was not including the file? I am getting a little confused here, XPS does not seem to support include directive of verilog. Has anyone tried it? I have now included the instantiation also in the main user_logic file, it now fails to resolve a function. Please mention if someone has in the past experienced the same problems.

Thanks, Bhanu

Bhanu Chandra wrote: ...

Make sure it gets included. The "Device utilization summary" after running XST should read: Selected Device : 3s200pq208-4

... Number of BRAMs: 1 out of 12 8% ...

Did you infer the BRAMs or did you instantiate them?

If the former, carefully check your synthesis report. Unfortunately, the tools will give you a polite Info: if your code did not properly infer a BRAM.

-a

I have Verilog code that uses include files, and it works with ISE. I stopped using them quite a while back because EDK lacks a method to tell it where to look for include files, and ISE just assumes that they are in its working directory unless told other wise.

Regards,

John McCaskill