Greetings everyone,
I've recently started working on FPGA designs and was wondering if there is a way to get timing reports and synthesis results from the Xilinx software that don't include I/O pin mapping. I'm trying to constrain several blocks for testing purposes, but these modules will all be internal to the design and won't be connected directly to the pins. However, it seems the tools automaically assume these connections, which is adding extra delay than what will really be there. Is there a way to tell the tool to ignore physical pin connections and use, say, simulated register I/O connections instead?
Sorry if this seems like a silly question, I'm still getting the hang of synthesis yet.
Thanks in advance, Jeremy