Hi, While porting hdl codes in xilinx, I synthesized using synplify with my constraints.Then I place& routed in xilinx-ISE the edif file (output of synplify). Now there are some timing errors coming in ise. Now I want to view the P&R 'ed file in synplify, which file I 've to load it in synplify. Is it possible to use synplify as the synthesis tool in ise (wher to set). One more doubt is in synplify I could see its mapping also. Again when I try to P&R the xilinx also maps. In the error in ISE it says try map
-timing option. Is it required even if we do auto constrain freq in synthesis using synplify. Please clarify Prakash