Design entries for FSM

Does anyone know how can one enter FSM in Xilinx sysnthesis tool. I have a FSM in a text format called the kiss2 format. It looks something like this:

file input.kiss2

--------------------------------------------start of file--------------------------- .i 2 .o 2 .p 8 .s 4

01 s0 s1 11 11 so s3 00 01 s1 s0 11 11 s1 s2 00 1- s2 s3 01 0- s2 s1 10 11 s3 s0 10 10 s3 s2 11

--------------------------------------------end of file--------------------------------- i= # of inputs o= # of outputs p= # of transitions s= # of states

01 so s1 11 = this is read as for input 01 and current state s0 the output is 11 and next state is s1. '-' means don't care

Does anyone know a way in which I can convert this to a format such that it can be entered into the Xilinx synthesis tool and I can get the FSM synthesized for further use my implementation

Reply to
Sue
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Are you a software guy? Do you use Verilog? Do you use VHDL? Do you know what a state machine is? Do you know how the HDL generally maps to hardware? Do you understand what the file above is communicating?

Answer us [sic] and we can answer you.

Reply to
John_H

Yes I am a SW guy

No I don't

Yes I do

Yes

No I don't know how this maps

Reply to
Sue

Six questions. One answer. Go away.

Reply to
John_H

Sorry I think something went wrong. I had answered all the questions you asked for. Let me answer it once again Please find the answers below your questions.

Yes I am a SW guy

No I don't

Yes I do

Yes

No I don't know how this maps

Yes I do

Reply to
Sue

Since you know what a state machine is, and you know what the particular state machine is that you're talking about and you know VHDL....why wouldn't you simply rewrite it in VHDL?

KJ

Reply to
KJ

I have very long and lenghty FSMs to work on. This is just a small example. Some of the benchmark circuits that I have to work on have 20 states and around 100 transitions so it is not feasible to hard code each FSM in VHDl. Instead if I can have a tool which takes FSM in a txt file format and converts it to a synthesizable format, it will be very useful. Any suggestions?

-Sue

Reply to
Sue

Thanks for providing some information about your real needs and your capabilities.

I don't think you'll find anything to take the kiss2 format and generate synthesizable code.

Given that you're a software person, you probably have the ability to quickly put together perl scripts or other parsers to generate simple VHDL case statements from the kiss2 format.

You understand what the state information is communicating so you only need to understand the VHDL case statement to get the mapping between your state machines and real hardware. If you do your own very simple parser, you can generate cut-and-paste text for very straight-forward case statements.

Go for it! It shouldn't take you long. I'm not a software guy so it

*would* take me a while.
Reply to
John_H

A quick Google of "Kiss2 to VHDL" shows that this has been done more than once. There is a paper on the subject on IEEE and I found a book review at:

formatting link

HTH, Gabor

Reply to
Gabor

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