Hello everyone,
I have encountered a rather strange behavior in one of my FPGA Designs. i have a DDR2 RAM controller (generated partly with the Memory Interface Generator) in a Xilinx Virtex-4 FX60. After startup it sends out some dummy patterns and reads them back to adjust the delay between issuing a command to the RAM and the execution. When I don't probe exactly these signals in the FPGA with Chipscope then this procedure is only executed sporadically, i.e. most times after configuration or a global reset the RAM controller never finishes its init-procedure (even when using an identical bit-file the success of the initialization can differ when configuring the FPGA another time). When I do use Chipscope however, it is executed everytime, so the use of it definitely influences the design. So the question is now, what could be the reason for it? Could it be a placement issue of the IODELAY elements used for the interface to the RAM or any other FPGA primitives that interface to it? If anyone had any guesses or ideas what could be the main influence I'd be happy to hear them, as I obviously would like to have the design running stably without needing Chipscope included.
Cheers, Michael