What's the best way to delay a signal? I want a certain control signal to appear X nano seconds after the rising edge of the clock.
Also, in VHDL, if I set the signal in a process on the rising edge, does the signal get updated at the next rising edge?
by the way, this is on a Virtex 4 and the control signal I want to delay is internal logic.
Hi,
John schrieb:
appear X nano seconds after the rising edge of the clock.
This is impossible for a fixed and guaranteed value of X. The only way you have is to use a flexible value for x. The output of a register will allways be visible a few ns after the rising edge of clk. If you need a signal to be within a given delay range, you could use gates with known delay (eg inverters) to introduce delay. But these delays are only tuneable to a certain degree due to gate and routing delays and you will only know a min and max delay for this path. This delay will vary over temperature, voltage, age and process. You need to verify, that synthesis didn't remove your delay gates, as they are typically without functionality.
signal get updated at the next rising edge?
if rising_edge(clk) then B
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