Hi,
I found that the delay value of the element FDDRCPE is 100 ns after running a timing simulation.
Is it supposed to be so high? (to confirm it, I also ran a separate simulation of this single element and with different clk frequencies)
FDDRCPE is "Dual Data Rate D Flip-Flop with Clock Enable and Asynchronous Preset and Clear", used when interfacing DDR with FPGA. It is present in the simlibs library.
I'm using ISE 8.1 (and found the same thing in 7.1 too)
If it is supposed to be that high, what may be the reason behind it?
See a related post here:
Thanks and Regards, Milind