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delay in altera cyclone about led

Dear all i write a simple test for led on altera cyclone board by jtag protocol

such as following: led[0] will shine with some frequence

reg [31:0] temp_count=0; reg direction=1;

parameter delay=23'h600000; always @( posedge clock)begin if(direction==1)begin temp_count=temp_count+1'b1; LED[0]=1; if(temp_count>=delay) begin direction=0; end end if(direction==0) begin temp_count=temp_count-1'b1; LED[0]=0; if(!(temp_count>0)) begin direction=1; end end end it did work after "few minutes" why it took "few minutes" to perform well, after i bured code into fpga completely thanks for reply

Sincerely Chronoer

Reply to
chronoer
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Most likely your synthesis tool ignores the 'reg direction = 1' initialization, and initializes it at zero instead. This results in down count from 0 to delay. which takes ~4 billion clock cycles.

Completely unrelated, but you should also use '

Reply to
Arlet

this time i add some codes:

initial begin direction

Reply to
chronoer

Reply to
Arlet

counter is indeed too large

after i reduced the counter

it worked as i thought

thank you very much

Reply to
chronoer
[ ... ]

In simulation, you're dealing with software, and initialization like this works fine.

After synthesis, you're dealing with hardware. If you want initialization to happen, you have to synthesize hardware to do it.

That usually means an input signal to your circuit. When it's asserted, you do initialization. When it's released, your circuit starts normal operation.

--
    Later,
    Jerry.

The universe is a figment of its own imagination.
Reply to
Jerry Coffin

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