Hi:
I have been tasked to build several custom laboratory instruments. One is a "safety system" for some engine combustion research labs that prevents the "engine controller" computer (a PC with a DIO board implementing a word generator driven by a shaft encoder on the engine) from issuing attempts to fire the engine for too long or at bad timings. This safety system has been delayed for several years due to other priorities.
The engine controller that we have now has problems with signal integrity and so its "patch panel" (the panel that buffers the DIO board signals to BNC connectors for connection to lab stuff) needs to be redone.
Additionally, the engine controller runs on MS-DOS, and so I'd like to update it to a modern architecture. Trouble is, this really isn't necessary because "if it works don't fix it." There are also no capabilities desired that it doesn't do already.
However, the engine controller does need to be connected to various SRS and Berkeley Nucleonics delay generator boxes for generating pulses in the time domain, as the engine controller only works in the shaft encoder's angular domain.
In summary then:
- Need a safety system.
- Need a new version of the engine controller patch panel.
- Would like but don't need a new engine controller.
- A future engine controller upgrade would be even better if it incorporated the safety system and time-domain delay generators.
I have decided that the logic required to implement the safety system (uses an absolute encoder to check timings against the quadrature encoder that drives the engine controller computer) is complicated enough that it should be based on a large CPLD or small FPGA. But if I base it on an FPGA, then it is only some additional HDL to implement the engine controller functions anyway.
So why not just make an engine controller with integrated safety features?
That's where I am heading.
One missing link: The time domain delay generators. Some stuff needs only microsecond resolution, so my present elementary logic skills can design those. But there are also nanosecond and 100ps resolution delays which we employ for some laser timing/intensified camera gating situations.
It is my understanding that an FPGA with DLLs and other clock timing/phasing features can be set up to give much finer resolution delays than could be achieved merely by counters at it's max clock rate. But the methods employed to do this and even an understanding of the finer clock management features of modern FPGAs are way beyond me. (I have just about mastered the much simpler world of CPLDs).
So my plan here is to think ahead. I want to design in an FPGA that is approachable with my present skills, but with enough surplus resources that I can expand the initial functionality (the safety system) into a full-blown engine controller with delay generators at a later time.
What FPGA architecture should I employ to implement a gadget which can do what I want (engine controller and safety system) while leaving a considerable amount of free logic resources for future advancement of its capabilities into the realm of delay generation to ns and sub-ns resolution?
I am looking at Spartan 3 development boards now. The Virtex stuff just seems way too overkill. There is no way I'd ever touch a million gates. But a few 10s of thousands or even a 200k FPGA might be suitable.
Would like to stick with Xilinx.
I know my logic demands are vaguely specified at this point. The idea is to get a rough idea of whether incorporating the fine resolution delays is worth planning for or not.
Thanks for comments.
Good day!