Decoupling V2P

I am little confused with the V2P decoupling guidelines. I am using a V2p7-ff896 part. It has 32 VCCINT pins and the the XST 7.1 suggest using a power rail scheme: .001uf - 34% .01uf - 31% .04uf - 18% .47uf - 9%

4.7uf - 3 % 470uf - 3%

The user guide and the Xilinx ml320 reference design use a .1uf for each pin and a bulk cap near the regulator. Similar with VCCAUX and VCCO. Which is the best way to follow?

Thanks for any help.

Reply to
Thomas
Loading thread data ...

God, this old chestnut again! So, in the old days, people used different values of capacitor in a decoupling scheme because they came in different types (ceramic, Al electrolytics etc.)and packages and so a combination provided a low impedance across a wide range of frequencies. For some reason, there are still people who think that it's a good idea to have a range of values, even though all the caps are the same size and type. Including, by the looks of it, the person who wrote the above recommendation. It's total nonsense. Some of these guys claim that using a range of caps is good because of the spread of self resonant frequencies. Bless them, they don't seem to understand that in the real world the caps are soldered onto a board and so the SRF effect is completely changed by the layout, the connections to the device etc. I use a lot of 0402 1uF X5R caps. I use a fair number of 0805 22uF X5R caps. Try reading this

formatting link
And this tool will calculate impedances for you.
formatting link

This is the way to go. The ML320 designers knew what they were doing.

Have fun, Syms.

Reply to
Symon

Symon, Thanks for your help. The murata capacitor selection tool is of great help. Thomas

Reply to
Thomas

TWO HUNDRED bypass caps?!!! That's crazy.

John

Reply to
John Larkin

Generally if you can follow the pyramid of values and numbers it is great. You will also find recommendations power plane structure and via structures if you dig. If you have not seen it yet have a look at Xilinx application note XAPP623 on power distribution as a starting point.

I would agree that reaching the numbers required is very difficult.You can get to the stage where the vias for the power capacitors effectively blocks the fanout of signals from the FPGA very significantly. You can help a bit by using capacitor arrays but even then board area of the packages and the vias is significant. We use a 0508 package containing 4 capacitors on our Broaddown2 and MINI-CAN products to help in this respect. You might be able to see them if you look at our website pictures of these products and how the capacitor layout forces the routing on the top surface tracking.

I would recommend at least roughly following the pyramid of values with smaller values closest to power pins and larger values further away. We did this on the products mentioned above with groupings at corners and centre row positions of the FPGA. If your product is already double sided then you can fit capacitors underneath the FPGA to ease the routing blockage but check that your board assembler is happy to do this. Some don't like parts straight underneath BGA or will claim a cost/yield impact on your assembly.

John Adair Enterpoint Ltd. - Home Of Low Cost FPGA Development Board MINI-CAN.

formatting link

Reply to
John Adair

John, Thanks for your comment. I had a previous design for which I followed the xapp623. It did work and it was for a Virtex part not V2P. Your recommendations are in sync with xapp 623 and ise 7.1 (xpower), not ml320 or the virtex2P users guide. And also contradicts Symons point of view. My main worry is why Xilinx is not following their own guidelines on their own designs. Or, I wish they make a revision to their documents when there is a change. May be it does n't matter either way! I do not have access to expensive board simulation tools or time to do it. Usually, I like following guidelines to be safe. By the way your board looks great. But, I prefer the

0402 cap for now where I have more placement flexibility. And I could place 0402 caps(atleast 2 per bank) right under the BGA, just to be safe.

Thomas

Reply to
Thomas

Thomas,

You bring up a valid point: why do we (Xilinx) sometimes not even follow our own best practices?

Well, for one, the design may be for a limited application where we do not feel the need to be as conservative as we would normally recomend.

Secondly, we may have designed that pcb using advanced SI tools which enabled us to minimize the power distribution system to just meet the requirements of that application.

And, sometimes we goof, and we do not do as good a job as we should have. After all, our pcb designers are human (big surprise?), and they can make a mistake if the design, requirements, and application are not clearly stated (sound familiar?). Maybe the review was skipped due to schedule issues ....

However, when we have a less than ideal pcb SI layout, it isn't long before reality sets in, and we have to go and deal with it.

If you have any issues with any of our boards, please email me directly.

The new sparse chevron packages in V4 with their demonstrated 8X advantage over other 90nm FPGA solutions has made some of these issues a whole lot easier to deal with!

Aust> John,

Reply to
austin

Thomas, John, OK, I'll have one last go at dispelling the 'pyramid of capacitors' myth. So, you've already downloaded the Murata impedance calculator right? The one from

formatting link
Draw the impedance curve for a 0402 X5R 1u 6.3v capacitor. Now draw the impedance for an 0603 X5R 2u2 6.3v cap. Notice how the 0402 cap has a lower impedance above about 8MHz. Now think about what you're trying to bypass. The logic in a V2PRO has risetimes of the order of 1ns (probably less), the I/Os can switch in about 3 or 4 ns. Lower impedance at

Reply to
Symon

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.