De-serializer using Xilinx DCM

I am working on a 'de-serializer' with Xilinx DCM. The single-bit input stream is sampled by an 8X clock. After 8 bits are stored the register, it activates a single-clock 'done' signal to inform the

1X system to retrieve the data. The data, of course, should only be read once.

I am thinking using a flag register to interface the two systems. The register is controlled by the 8X clock. The done signal sets the flag and the 1X system resets the flag after read. Since DCM is used, presumably there is no meta-stability issue.

Please comment whether this approach is feasible or provide pointer to some reference designs.

Thanks in advance.

S. C.

Reply to
fp
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Reply to
Peter Alfke

In UART, the system clock rate is much higher than the serial input and the system can do 'oversampling'. The situation is reverse in my application, in which the serial input rate is much higher (and that's why a DFS and 8X clock is used).

Reply to
fp

And the 8x clock is syncrhonized to the incoming bitstream how?

Andy

fp wrote:

Reply to
Andy

Reply to
Peter Alfke

Thanks for your replies. This is just an exercise for myself. Currently I am trying to learn the design of high-speed serial interface. Before looking at the nasty analog aspects, such as clock skew and signal integrity issues, I would like to first to understand the operation the digital part. Let me just assume that system clock is 25 MHz and the serial input is synchronized at 200 MHz.

Reply to
fp

Reply to
Peter Alfke

XAPP224 XAPP671

Also, Antti has done something with the MGTs involving oversampling. He posted it here a while back. HTH, Syms. p.s. BTW, there's nothing nasty about analog projects and SI aspects, some of us make a reasonably decent living out of this type of engineering! ;-)

Reply to
Symon

Thanks for your help.

"Nasty" means hard and good money :)

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Reply to
fp

Peter, If I understood his original post correctly, the first question is what he was asking of you, as I believe he intends to derive both clocks from the same DCM.

The answer is it depends on the set up of the DCM. if you use the clkdv outputs and supply the DCM with 200 MHz (0r 100MHz using the clk2x output), the clocks will be pretty well aligned in most cases. If you use a 25MHz clock and the clkfx to multiply up, the clkfx will exhibit a bit of jitter and the alignment may not be perfect (assuming the Mand D are set for an integer multiplication of the clock). So in an ideal world, you should be able to cross between the domains...

However, it would be prudent to treat the clock domain crossings more carefully. Jitter on the input clock can lead to a greater separation between the edges that could get you into trouble (I ran into a case like this when SpartanII was new, where we saw clock jitter on the DLL input result in a large skew - close to 1ns - between the 1x and 2x clocks out of the same DLL, and most of the clock jitter was not visible at the clock input pin because it was getting introduced by many outputs on the same bank as the clock input switching on the same clock edge).

Reply to
Ray Andraka

question

Reply to
Peter Alfke

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