I am working on a 'de-serializer' with Xilinx DCM. The single-bit input stream is sampled by an 8X clock. After 8 bits are stored the register, it activates a single-clock 'done' signal to inform the
1X system to retrieve the data. The data, of course, should only be read once.I am thinking using a flag register to interface the two systems. The register is controlled by the 8X clock. The done signal sets the flag and the 1X system resets the flag after read. Since DCM is used, presumably there is no meta-stability issue.
Please comment whether this approach is feasible or provide pointer to some reference designs.
Thanks in advance.
S. C.