I am writing veerilog code for DDR2 SDRAM controller using the micron memory module and I want to implement it on Virtex-4 FPGA.......but I am a new comer to verilog and due to time constraints I am afraid that i won't be able to write the complete code(complete all modules)......so can any one provide me a synthesizable code......the one i cud get from the xilinx web site( reference design) is not synthesizable.....plz help
Anand" schrieb im Newsbeitrag news: snipped-for-privacy@g44g2000cwa.googlegroups.com...
just start Xilinx memory interface generator (MIG) click a few times and you get synthesizeable and work code inclusive FGPA toplevel test fixture. then assing pins in UCF and ready you are!
-- Antti Lukats http://www.xilant.com
Anand schrieb:
Hi,
concerning DDR2 you will not be able to just download a bunch of Vlog / VHDL press the button and your done. In DDR2 the IO-Level, the way you interconnect the DDR2 device and the IO-Logic of your DDR2 controller heavily depend on the ASIC / FPGA infrastructure you have. So for example for Virtex-IV on the IO-Level it will not be same 'behavioral' code as it is for Altera Cyclone / Stratix-II devices.
- Data Capturing, Clocking etc. depend on the FPGA you use.
By the way, what did you download and what is not synthesizable. The more info we got, the better we may be able to help ...
Cheers Markus
P.S. DDR2 and FPGA is NOT an easy task...
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Antti Lukats schrieb:
Hi Antti,
are you really using this approach click-and-you-are-done for productive and mission critical industry DDR-II designs running at ~ 500 MBit data rate?
Markus
Does it matter to the original poster?
Thank you all for the info....now this is what I want and what I have done.....Plz help me further
I am doing only a project titled "RTL coding of DDR2 SDRAM memory controller" so what I want is only a verilog code which is synthesizable. I myself tried writing some of the modules but the problem is that I am new to verilog and there is a time constraint, so I need some help in the coding part.
Moreover I downloaded the MIG tool V1.4 from the xilinx site.....
now I have the ISE8.1i webpack version and when I install MIG1.4 it doesn't work (or i donno how to work with it...plz help) Can someone tell me how to work with it...in a detailed way...I mean if I double click the tool its not opening!!! How shud I go abt it.....can someone plz read the code available in the link I provided( u have to download it...itz some 24mb zip file) and tell me whether it is correct and synthesizable...when I imported all these files directly into Mentor Graphics FPGA Advantage tool it shows a lot of errors....what changes shud I do...plz read the code and help me asap....thanq all a lot.
Anand,
I think it is a terrible idea to start with DDR2 SDRAM controller if you have absolutely NO idea of how to use a HDL and the corresponding tools in a correct manner. First try to learn the HDL and the use of your tools.
Rgds Andr=E9
hello ppl....can neone plz help me out...I guess i have done some homework regarding my tools....plz help me out guys
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