DDR2 Memory Controller : IOSTANDARD

Well ... the message is pretty clear I think ...

ERROR:Place:311 - The IOB DDR_DQS is locked to site IOB_X0Y5 in bank 7. This violates the SelectIO banking rules. Other incompatible IOBs may be locked to the same bank, or this IOB may be illegally locked to a Vref site.

"Other incompatible IOBs may be locked to the same bank,"

Well ... If you have a IOB in the same bank with a io standard requiring 2.5V voltage that would be bad. So check the IO standard for all the other pins of the same bank. They _at_ least should be set to some IO standard using a 1.8v vccio.

"may be illegally locked to a Vref site."

If you read the User Guide about SelectIO and the part about DIFF_SSTLII standard, you should know that the vref pins must be connected to the ... vref ... So obviously you can't use them as data/dqs pins. Check that your board doesn't do that.

Sylvain

Thanks.

I only have 2 types of IOSTANDARD in the same bank, SSTL18_II_DCI and DIFF_SSTL18_II_DCI. Both requires 1.8V. However, it was found that ISE had assigned LVCOMS25 to the pin that I had specified to be DIFF_SSTL18_II_DCI. This ended up with both 2.5V and 1.8V in the same bank. How can I fix this problem?

Thanks.

DIFF_SSTL18_II_DCI. Both requires 1.8V. However, it was found that ISE had assigned LVCOMS25 to the pin that I had specified to be DIFF_SSTL18_II_DCI. This ended up with both 2.5V and 1.8V in the same bank. How can I fix this problem?

Did you use a differential output buffer for DQS ?

DIFF_SSTL18_II_DCI. Both requires 1.8V. However, it was found that ISE had assigned LVCOMS25 to the pin that I had specified to be DIFF_SSTL18_II_DCI. This ended up with both 2.5V and 1.8V in the same bank. How can I fix this problem?

Hi, thanks.

I had checked the UCF file and there was no more than one assignment for the same pin. When I specified that IOSTNADARD to SSTL18_II_DCI, it worked fine. But it went wrong when the IOSTANDARD is DIFF_SSTL18_II_DCI. Seems the ISE can recognize this and set the IOSTANDARD to the default LVCMOS25. I am correct to say that? Is this the problem with ISE? I am using ISE 8.1i and my FPGA device is Virtex-4 XC4VFX60.

Please advice. Thanks.

Please ref to UG075.pdf from xilinx. check your package and you'll find that problem.

Virtex-4 XC4VFX60? when use ISE, we also need to know the package. then you get the p> Hi, thanks.

same pin. When I specified that IOSTNADARD to SSTL18_II_DCI, it worked fine. But it went wrong when the IOSTANDARD is DIFF_SSTL18_II_DCI. Seems the ISE can recognize this and set the IOSTANDARD to the default LVCMOS25. I am correct to say that? Is this the problem with ISE? I am using ISE 8.1i and my FPGA device is Virtex-4 XC4VFX60.

Thanks.

I had checked the document and the package that I am using is Virtex-4 XC4VFX60-10FF1152. This had been specified correctly in ISE. I still can't figure out any problem from UG075. Please advice. Thanks.

ref to UG070.pdf, page 286 : Rules for Combining I/O Standards in the Same Bank

and check signals > Thanks.

XC4VFX60-10FF1152. This had been specified correctly in ISE. I still can't figure out any problem from UG075. Please advice. Thanks.

I only used DIFF_SSTL18_II_DCI and SSTL18_II_DCI in bank 7. This satisfy the rules. But ISE didn't assign DIFF_SSTL18_II_DCI for the pins. It turned out to assign the default LVCOMS25 on those pin, which had violated the rules. It seems like I was not allowed to specify DIFF_SSTL18_II_DCI. So how should I fix this problem? Thanks.

rules. But ISE didn't assign DIFF_SSTL18_II_DCI for the pins. It turned out to assign the default LVCOMS25 on those pin, which had violated the rules. It seems like I was not allowed to specify DIFF_SSTL18_II_DCI. So how should I fix this problem? Thanks.

Do you 1) have an OBUFDS driving the two differential pins? 2) have the _P and _N pins in the proper differential pair per available Xilinx IOBs? For any pin, there is at most one other pin that can be used as the other half of the differential pair.

Zyan, can you please send me a zip file with the following files design.ngd design.ucf ngdbuild.log map.log (or design.mrp) par.log

I would like to take a look Aurash

zyan wrote:

rules. But ISE didn't assign DIFF_SSTL18_II_DCI for the pins. It turned out to assign the default LVCOMS25 on those pin, which had violated the rules. It seems like I was not allowed to specify DIFF_SSTL18_II_DCI. So how should I fix this problem? Thanks.