DDR2 dqs pin // virtex4

I don't understand - you have an error in the ucf file, you changed the ucf file, it fixed the problem but you want a different solution so that you don't have the change the ucf file?

Your VHDL code directly instantiates the IOB. ISE 'knows' to which pins the IO and IOB outputs of IOBUFDS can connect. Your VHDL connects the DQS pins using vector notation, which is good because it is concise and understandable. If you wanted to change the VHDL, you could instantiate the IOBUFDS of each DQS separately. For the DQS that has the error in the ucf, change the signal names to match the ucf. This will make an inverted DQS output, so be sure to invert that DQS bit somewhere in the DQS generation logic. Check the timing carefully to make sure that the inversion doesn't cause any timing errors. Finally, put in a comment explaining why you made this change.

I had a similar problem on a design, except that the PC board had an error and the N FPGA output went to a P SDRAM input; the P FPGA output went to the N SDRAM input. I inverted the signal before the IOB then commented it carefully so that months later I wouldn't wonder why that signal was coded differently than the rest. (It was my job to check to PCB artwork before fab, too.)

Thank you for comment. I need to change my file.ucf to route the FPGA. So, the information is opposite. DQS0 should have the same information as DQS1 (I use Lower and Upper byte in memory). But with this chnage in ucf, DQS0 = DQS1_N.

I changed IOBUFDS for only DQS1, DSQ1_N I invert DQS1 bit in the DQS1 generation logic, but I have no result in the board (the source code was tested in a other DDR2 memory with success).

I don't know if the problem is a timing or other.

Could you indicate me an example (please find the code in my first mail) to invert DQS1 bit in the DQS1 generation logic. Thanks lot in advance.

Best regards, Benoit.

"Joseph Samson" a écrit dans le message news:

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I'm sorry that I still don't understand what you're telling me. Can you explain why fixing the ucf file isn't the correct solution and can you please tell me what the original ISE error was?

Can you explain this in much more detail? What do you mean that the source code was tested in another DDR2 memory with success?

My VHDL is rusty, how about: iobuf_dqs : IOBUFDS port map ( O => dqs1_in, IO => DDR_DQS1, IOB => DDR_DQS1_L, I => not dqs1_out, T => ctrl_dqs_en_r1 );

Thank Joseph for your comment.

ISE 'knows' to which pins the IO and IOB outputs of IOBUFDS can connect. I found the solution to not modify my ucf pinout, and not modify the logic value of DQS and DQS_N. I changed the IOBUFDS, and used IOBUF and ODDR. With ISE, I can connect : DQS_N => PIN IO_P DQS => PIN IO_N

In ucf , use IOSTANDART = SSTL18_II (not DIFF_SSTL18_DCI).

I routed this solution, and the test is OK on the board.

Benoit.

"Joseph Sams> > Thank you for comment.

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