DDR2 controller V4 vs V5 differences ?

Did you use the same speed in your previous design or ist it slower now than it was before? Or is the routing maybe different (shorter traces)?

I have a DDR2-design on a Virtex4 as well, running at 125MHz, and the calibration doesn't work there because the maximum delay the IDELAY can do is 5ns. I don't remember the exact details, but I think during calibration they delay the DQS until they detect 2 edges to measure the cycle time and match it to the FPGA-internal clock, and then set the delay for the data pins accordingly, so there is a phase difference of

90 degrees.

In my case the delaying for the strobes didn't work, the calibration would just never find the second edge because it could not delay by more than 5 ns. If you have very short traces between FPGA and DRAM giving you a delay of maybe 200ps, you have to delay the strobe for another

3.2ns just to find the first edge, and then another 4ns (if you're running at 125MHz) to find the second edge, which is a total of 7.2ns, which the IDLEAY can't give you. So in my case the calibration just would run to the maximum and then give up.

I turned it off and fixed the delays manually to get ariound this.

HTH, Sean

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It's the same speed as on the V4. I tried 250 MHz and 200 MHz. (DDR2 clock). The board are completely different and I don't know much except they matched the trace length ... (For others infos I have the schema but not the pcb design files).

But I used that controller without much trouble on 2 v4 board. And here I just tried two V5 board without success ...

When looking with chipscope what it captures, I can't see a signle read success ...

Sylvain

In Virtex-5 the BUFIO delay is larger which alters the initial position of the DQ relative to the DQS. The existing Virtex-4 SERDES DDR2 algorithm (XAPP721/723) won't handle this.

What's the need for the half frequency design in Virtex-5? Could you use the full frequency design with a shim to conver the data to half speed?

In response to the issue with the calibration algorithm running out of taps, the current algorithm can detect the single edge situation at lower frequencies and move the taps away from the edge appropriately to achieve reliable operation.

Hi,

Thanks for the info, at least that gives some leads.

How much larger ? How could that be adapted ? Wouldn't changing the default value of the delay to the trick ?

The thing is that we customized this controller to fit our needs and we'd rather stick to it. It also has a much easier time meeting timing that the V5 controller because a lot of the logic runs at half the frequency.

Sylvain

Hi Sylvain,

The BUFIO delay is now up to about 600 ps longer. We haven't looked at workarounds for this, but it must be compensated for. I am sure you could find something.

What frequency are your running your interface? What width and what speed grade do you use? The Virtex-5 DDR2 controller is getting some speed improvements shortly that might help your timing. I realize that it won't help with your modifications, so it may not be a reasonable alternative for you.

Regards, John

"Sylvain Munaut " wrote in message news: snipped-for-privacy@50g2000hsm.googlegroups.com...

I've just tried setting an initial delay of 600 ps on the DQ lines but without sucess ...

I do my tests at 200 MHz currently. But in the final design it needs to run at 250.

We are on the slowest speed grades. Currently we need a 8 bit width. But soon we'll need up to 64 bits.

Do you have an estimated date ?

At least I get an explanation on why it might fail ...

Sylvain