DDR Simulation Model

Kingston makes DIMMs not RAMs. You can find RAM models on Micron's website.

Hi S, When you write data into Block RAM of Xilinx FPGA, you provide address and data in the same clock. When reading, first clock is to provide address, then reading its data from data bus on second clock due to one clock delay of Block RAM.

DDR RAM is totally different from Block RAM of Xilinx. It has some defined bus activities to get data written or read. You cannot directly read or write by PowerPC. There must be some logic between them to access approprite data.

You must read its manual carefully and understand its read and write rules that is at least 20 full pages long.

Weng

Thanks for your answer. I have taken a look at

(Design Support etc.) The problem is that I can not find a module that has the specifications of the RAM I use in my design. The KVR2666X64C25//256 has the following specs (according to the data sheet):

- 256MB 32M x 64-Bit

- DDR266

- CL2.5

- 184-Pin DIMM

There is no module on Micron's site that has these specs. Every DDR266- Module has a CL2.0. I can only choose between pin count 66 and 66- ball. A depth of 256 MB is not available for DDR266. I have looked at my design. There are 106 pins used for the interface between the PLB DDR controller and the RAM module. So a pin count of

66 does not seem useful to me. I am sorry if ask very stupid questions, but it is the first time I use DDR SDRAM.

Hi Tianxiang,

thanks for your answer. There is a DDR controller in my design. All components are connected via PLB bus. So everything I have to do is to use the PLB protocol. The controller will handle the rest. What I do not understand is that some data is written and read correctly. There is only one 64 bit word which is missing. The PowerPC starts reading at the base address of the DDR RAM (0x00000000). I use a simple pointer PMEM and assign the value in PMEM to another variable. After the data has been read from the RAM PMEM is increased by 4 (32 bit data width). This works until PMEM is 1152. Then the error occurs. After this error everthing looks fine again.

I have taken a look at the RAM Module. There is some more information on the RAM chips:

0516 1-1 MT 46V32M8 TG -5B G

What does this mean and how can I use it to find the correct simulation model?

Well :

TYpe KVR266X64C25 in Google Get the spec sheet (first link) Count chips on module (result : 16 chips) So, it has 16x 32Mx4-bit chips making 32Mx64 bits

Then, either get a module and look at what chips it actually uses, or : Go to Micron's site and search 32Mx4-bit, CL2.5 modules

MT46V32M4P-75 MT46V32M4TG-75

Hint : those are DDR266B, not DDR266

That's because you got a Kingston module ;) not Micron

That's because there are 16 chips on your Kingston, not 1. If you check the pinout of the 184-pin DDR module you'll notice that there are something like 106 useful pins, the rest is power supply and ground...

Are you routing the PCB ?

Sorry, did not read this before writing the previous email ;)

Look for a model of a Micron chip like :

MT46V32M8-5BG

or something. Note you'll have to instantiate the model 16 times (since you got 16 chips on your RAM stick) and connect the nets accordingly.

This is a Micron Technology RAM; look for a Micron model which matches

46V32M8 - or find how Micron translate device markings to part numbers.

In the event you need a VHDL model, Micron may not offer VHDL models for newer devices for some reason, you may need a model from the Hynix equivalent part.

Re: the error at pointer = 1152 - this is an odd number. Does this error coincide with a refresh cycle?

- Brian

Hi Brian,

I have no idea since I am currently testing the design on the board. After I have a simulation model for the DDR RAM I can check this in the simulation.

Hi PFC and Brian,

thanks alot for your answers. I am now about to find out, which RAM model I can use and ... believe it or not - I have some trouble. ;-)

The datasheet of the Kingston DIMM says that this is DDR266 with a clock cycle time of 7.5 ns. CL = 2.5

Like Brian already said the RAM modules are Micron products. According to the Micron datasheets TG -5B G means that this is a RAM module with a clock cycle time of 5.0 ns. CL = 3.0. The Appendix G means Revision x4, x8. I have no idea what this means. It does not seem to be very important. The problem is that TG -5B is only available for DDR400B on the Micron page. There are two models available:

MT46V32M8P-5B MT46V32M8TG-5B

The only difference is the package which should not be important for the simulation. So the question is: Can I use this model? I am asking this question before I give it a try, because I know it will be a lot of fun to implement this model in my Xilinx EDK design.

You'll have to use a 'generate' statement to set up an array of Micron DRAM models so that it matches the configuration of the Kingston DIMM. There are some `defines (in the Verilog version) that allow you to configure the particular flavor of DRAM.

If you are doing an RTL simulation (i.e., no IDELAY UNISIMs) you will be assuming that your timing is correct. To get a more accurate model, you need to use wires with bidirectional delays to model the PCB and IOB delay. One of the biggest problems with making your own DRAM interface is getting the return data to line up with your local clock. -Kevin

Clocking it at 5ns, it would need CL=3.0. I believe this means at 7.5ns it should support CL=2.5 comfortably; check the datasheet to confirm that you can set the Mode Register correctly for the CL value you want.

Is it available in the language you are using? If it's only available in Verilog and EDK is still only VHDL, your simulator needs to support both languages. I don't know why Micron omit some models in VHDL.

Otherwise you can still simulate without it, to check for collisions between refresh and access.

- Brian

Okay, meanwhile I got the DDR model implemented in my design. The testbench compiles without errors and warnings and...the DDR model does not work. In fact every write access is accepted. But when it comes to read accesses an error occurs. I can see in the waveform that the requested data appears on the DDR_DQ bus and is transmitted to the DDR controller. But it never appears on the PLB bus.

The following message is written in the transcript:

** Warning: PLB IPIF data phase timeout assertion.... Addressed Target did not respond! # Time: 515160 ns Iteration: 4 Instance: /xup_morpheus7_wrapper/ xup_morpheus7_1/ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ ddr_256mb_32mx64_rank1_row13_col10_cl2_5/wo_ecc/plb_ipif_i/ i_slave_attachment

But when I take a look at the waveform the signals of the master/slave- protocol look fine to me. The DDR controller accepts the read request from my design. And after some time the the acknowledge signal is assigned (bus2ip_mstrdack = '1' and bus2ip_mstlastack = '1'). So even the time limit which causes the message is exceeded the DDR controller handles the read request. But the transmitted data is always

0x00000000.

Does anybody know, how to solve this problem? Is it a timing issue? I use the SG75 configuration for my model. The parameters are below or equal to the parameters of the Kingston module. I think this should work, shouldn't it? I also created the RAM module by myself. So I did not use the DIMM file parameters. I will try to compile a complete DIMM instead of 8 single RAM modules. But I don't think that this will change a lot since I copied the signals assignments from the DIMM file.