Hi all.
Is there, somewhere, an open-source Verilog (or VHDL, but Verilog is preferred) module of a DDR1/2/3 SDRAM that can be used for simulating a memory chip/module??
I want to build a memory controller, but want to do as much as possible in the simulator and hopefully only verify the correctness of it in silicon.
You might check with the memory makers. I know they have IBIS models now, but at one time you could get HDL simulation models I believe. If you are using this as a reference to test your memory controller, it will be useful to have a verified memory model rather than rolling your own which will likely have similar conceptual mistakes as your memory controller.
Which part are you looking at using?
-- Rick
No particular parts at this point. I'm sort-of aiming at random mass produced DIMM modules, but honestly I still haven't settled on the interface yet. I'd like to use DDR1 because the memory clients are not expected to have a very high throughput so the newer interfaces are basically overkill. However, I'm not sure if those old modules will be available over the next decade (or two, or three).
BTW, I found something over at Micron. At first glance it seems usable, but I'll have to read it to be sure.
Trying to second-guess the PC market is a fool's game.
You may want to look around and see if anything is marketed toward embedded systems -- there are plenty of those that do use DRAM, and people doing the systems generally like to see long life parts.
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com
There will probably be chip availability for a while, but prices for modules are heading skywards. So depends how price sensitive you are, and how much you need to push the envelope. 2GB DDR1 is expensive, 256MB DDR1 isn't because there are end of line modules floating around. However I imagine that's unlikely to be the case for the next decade. I'd guess going with DDR3 would buy you a decade over DDR1 - but obviously more complex.
If you aren't doing high throughput can you do SDRAM? That market seems to be more stable, and the controllers are easier.
Theo
W dniu ?roda, 30 wrze?nia 2015 22:38:11 UTC+1 u?ytkownik Ale ksandar Kuktin napisa?:
Have you tried the FMF models:
Regards, Wojtek
I did a couple of DDR controllers and used Verilog models from Micron and t hey worked really well. I think I made one change to the source. The mode l was really slow, so I put in a Modelsim directive to allocate the main ar ray as a sparse matrix, so it would only allocate RAM (on the simulating co mputer) as it was accessed. The models caught all sorts of obscure errors, like not waiting 3.5 cycles to access a row in the same bank of a row that was accessed within the last fortnight or whatever.
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