DDR SDRAM Controller

Thanks to all!

I simulated my design indeed using Micron memory models (I us mt8vddt1664a memory model for simulation - it's not exactly my model bu seems to be closed enough for me) and as I wrote before it worked jus fine. But I did not use the FPGA netlist in my simulation. So a snipped-for-privacy@web.de said I'd simulated the VHDL description but not th synthesis result. I am going to simulate the synthesis results (I'll do i tomorrow because first I have to find out how to do it. I've never done i before). Does somebody have a good link about it? So I'm googling around I'll write about results tomorrow.

I am open to any other ideas.

Best, Ada

One thing I did not mention that *has* given me a great deal of grief on DDR is Vref. DDR requires this to be V(mem) / 2 and the clock crossings have to be within a tight range of this, to say nothing of the other signals.

if Vref is produced by a resistive divider with a cap, you might have an issue with just *some* memory sticks - they pull more from Vref than the divider can stand (it's not stiff enough) and you'll get all sorts of flaky (particularly read) behaviour. The standard behaviour of devices is such that the current drawn from Vref is temperature dependent, too, which you are seeing.

Stick a scope probe on Vref somewhere with a 'bad' stick and see if it remains at the proper level (or if it even gets to the proper level).

Cheers

PeteS

Another point on using Virtex II and Vref. The tools will automatically determine whether Vref is required for a particular bank based on the inputs to that bank. I have had a problem in the past where I did not realize that my SSTL signals on one bank were all outputs (Address and Control lines). For this bank, I had the Vref pins tied to a source with a relatively high impedance. The Vref pins were not required for Vref on that bank and so the tools automatically defaulted them to weak pullups. The half dozen "weak" pullups were enough to bring the Vref up to almost 2 volts. This is worth checking if you are not using all of the connections on the board, for example leaving out a feedback input. If you inadvertently free up the Vref pins on a bank they could get you in trouble. In my design I fixed the problem by setting the BitGen defaults to "Float" for unused IOB pins.

Regards, Gabor

Hi all,

sorry for keeping silence. I tried Post-Synthesis simulation with ModelSi but I had an error:

# ** Error: Timing Violation Error : RST on instance * must be asserte for 3 CLKIN clock cycles. # Time: 8100 ps Iteration: 1 Process /tbx_top/i_top/i_ddr_sdr/dcm0/dcm_inst1/check_rst_width File C:/Programs/Xilinx/vhdl/src/unisims/unisim_VITAL.vhd

This problem is caused due to Xilinx libraries. In the testbench, the DC Reset is initially defined as "x",then it changes to "1". This initia transition is evaluated as a valid transition, and starts the DCM Rese lenght check from this transition, therefore causing the ERROR.

So Xilinx proposes to update the software libraries. I did it but it di not help. Does anyone have an idea how to fix it? Any case I do not think I have to spend too much effort in order to brin the simulation to work because it's just a simulation. Nobody coul guarantee that even if simulation works it would work with the real board So I have to concentrate on a real board.

I asked AVNET about connecting an oscilloscope to the board but no answe till now. And I have not found anything related to their boards and osc connections in Internet.

Does anyone have a working DDR SDRAM controller example? Or some othe ideas related to my problem? I would really appreciate it.

And one more question. I am using 125MHz FPGA clock and I am giving clock with the same frequency (generated with DCM primitives ) to the DDR SDRAM I think it's ok but maybe I am mistaken. Does someone have othe suggestions?

Best, Ada

Hi ada,

How do you generate the Reset, do you you generate it in the testbench ?

Rgds Andr=E9

Yes, you are right.

But performing a timing simulation you can at least say that your FPGA generates the timings correctly. For that purpose I think it could be an advantage to use a simple test case, for writing data to DDR memory and reading it back (simplified data path) Once proved you can concentrate on functional simulation and static timing analysis.

Rgds Andr=E9

Hello,

there is a problem with the reset signal in DCMs but it's nothing to d with my design. I define rst signal for dcm in my ddr_sdr module (not i my testbench) and initialize it with '0' but it's not the point. The poin is Xilinx libraries were buggy. Look her

and here

Any case I ignored this error and also changed some libraries and DC locked. So now I could say that Post Synthesis looked ok. I have also jus done Post-Place & Route Simulation (with -sdfmax parameter) and I had lot of warnings:

1) for all CKEs Warning: CKE Setup time violation -- tIS 2) for all ddr_sdr_data_lo1_q (it's a low part of buffered data bus) Warning: /X_FF SETUP X VIOLATION ON I WITH RESPECT TO CLK; # Expected := 0.182 ns; Observed := 0.129 ns; At : 207478.794 ns 3) for some ddr_sdr_data_hi_q (it's a high part of buffered data bus) # ** Warning: /X_FF HOLD Low VIOLATION ON CE WITH RESPECT TO CLK; # Expected := 0.028 ns; Observed := 0.016 ns; At : 207494.807 ns

I also saw lots of data glitches on data bus. But I have to look at th simulation results more detailed and it's already too late. I think could tell more tomorrow.

Till tomorrow.

Hi all,

Post-Place & Route Simulation is ok now (I had some warnings due to dat glitches but I fixed it and everything works fine). Anyway there is n progress with the board :( Do not know what I could possibly do. It seem without an osci I am really lost. Or someone has an idea? I would b really glad to hear any suggestions!

Best, Ada

Hi Ada,

ask Avnet if there is some DDR controller IP core evaluation bit stream available for the board so that you can check whether DDR memory accesses are possible and correct at all. If they are correct then you know at least that you have to analyze your own controller.

Rgds Andr=E9

Do you get DQS from the DDR memory if you send READ commands to the memory ?

Rgds Andr=E9

snipped-for-privacy@web.de schrieb:

Ok, you already answered that question.

Avnet provides a test DDR SDRAM controller bit stream with their boards an it works. That's why I'm sure it's my controller problem. But I how could find out it if even post-place&route simulation works fine? I'm out o ideas.

What are you doing with the data you read from the memory ? Could it be that they are not used so that the synthesis tool optimizes the complete read path away ?

Rgds Andr=E9

Thanks that you're trying to help me. data is my 64-bit data bus. So a you could see below I'm puting some data on the data bus during write o using output buffer primitives and buffer the data bus using inpit buffer for read op.

GEN_D3: for n in 0 to DDR_DATA_WIDTH-1 generate

DQ_OBUFT : OBUFT_SSTL2_II port map ( I => d2sdr(n), T => tristate_q(n), O => data(n) );

DQ_IBUF : IBUF_SSTL2_II port map ( I => data(n), O => read_data(n) );

end generate GEN_D3;

After I'm fetching low- and hi-words from the buffered data bu (read_data) on rising and falling edges of the clock. So it does not see that the synthesis tool (XSE in my case) optimizes the complete read pat away.

Hi all, could someone give me a tip about using DCMs?

I have seen many different memory interface clocking schemes bu unfortunately I did not find any explanation related to a general schem just different examples. Could someone explain it to me? I'd like to kno in which case which scheme I should use.

I think I really have a clock synchronization problems but I can not chec it because I do not have an osci. I have 2 memory feedback clocks (feedback output and feedback input) clk_ddr_fb_out and clk_ddr_fb_in correspondingly. So clk_ddr_fb_out i connected to ddr_clk and driven into the memory and clk_ddr_fb_in i driven from the memory to my design. In my design two separate DCMs ar being used, one internal DCM for the memory controller design inside th FPGA and the other external DCM to forward clocks to the external memor device. Look at this picture.

But in this case DCM1 does not lock:( Am I doing something wrong? An ideas?