DDR-ram interface (xapp200)

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Hi,

I'm working on a University project that requires ddr-ram interfaced to a
Vertex-EM device.  I am basing my design off xapp200 from xilinx.  The
design uses DLLs to deskew the system clock and ddr-ram clock.  The signal
fed back to the DLLs (sys_clk_fb) is apparently the ddr clk.  What I don't
understand is where I take this signal from.  Should I have tracks on my PCB
comming back from the ddr-ram chips to inputs on the fpga?  Or can the
feedback signal come from inside the fpga?

I am a little lost as to how the DLLs manage to sychronise the two clocks.
Any help would be appreciated.

Thanks.

Michael.



Re: DDR-ram interface (xapp200)
Thanks for the help Bob.  I think I know what I have to do.

Cheers,

Michael.

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Re: DDR-ram interface (xapp200)
I highly recommend the section on Eliminating Clock Skew in XAPP462:  Using
Digital Clock Managers (DCMs) in Spartan-3 FPGAs.  The section begins on the
bottom of page 25.
http://www.xilinx.com/xapp/xapp462.pdf

Although the application note is written for Spartan-3 FPGAs, the DCM is
functionally very similar to Virtex-II and Virtex-II Pro.  The differences
are also described in the application note.
---------------------------------
Steven K. Knapp
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3:  Make it Your ASIC

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PCB



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