DDR Memory Access Interfact by Virtex-4 FX12

Hi,

I just used MIG to generate the memory access interface to the DDR memory. But now I am confused as to how to used the files?

Should I include in my project the .vhd files and then declare a component of the library and write my own accessing code to the interface? Or whatever?

Does anybody know whether there is any reference design on this?

Thank you so much! Roger

Reply to
agou
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"agou" schrieb im Newsbeitrag news: snipped-for-privacy@g43g2000cwa.googlegroups.com...

we had the same issue and when we asked help here no one responded.

so we had the same issue, generated a DDR2 thing with MIG, then implemented it in FPGA connected the status LED and then what?

I was looking at the MIG datasheet, and it was clearly saying that the DCR (dynamic command reqest) on the upper address lines is optional, but it actually is not dont care, it does matter.

so for the DDR2 you plave 101 or 100 on upper address bíts (for read or write) set address set AF_WREN and then the DDR2 IP core works

but there doesnt seem to be any reference design at all so you need some kind of glue yourself

the above is for DDR2 generated by MIG, the DDR may be little different but you most likely also need the same toplevel glue and check the datasheet for dynamic command, etc

Antti

Reply to
Antti Lukats

Hi, Antti

Thanks! I am really a newbie on FPGA. So could you tell me how did you make it? Did you imported the project all the .vhd files? And then declare yourself the component and ports? Design the logic to start the read and write? And so on? bla bla

Thanks! Roger

Reply to
agou

"agou" schrieb im Newsbeitrag news: snipped-for-privacy@g43g2000cwa.googlegroups.com...

well I dont know the DDR with MIG only the DDR2, in that case it generates the FPGA top test module that includes a special FPGA synthesizeable test unit. the test unit makes some writes and reads and has an LED for pass fail status.

so I just created a ISE project and added all the files, fixed the UCF and looked if my status LED is on or off.

for MIG generated DDR I dont know if the testbench is generated or not, so if not then you need to write it yourself.

if you are really an FPGA newbie then its better not fuzzle around with MIG if you only need DDR, the reason we used MIG was the support for DDR2 memories.

for DDR just use EDK to generate a system and verify that it works. Later you can decicde what DDR memory core to use.

Antti

Reply to
Antti Lukats

Thank you for your suggestions.

Reply to
agou

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