DDR Lines on FPGA : Physical considerations

I'd suggest looking at the results with the series resistor at the S3 driver before the transmission line for a baseline and then moved to the end of the transmission line before the split for a comparison. You may see very little difference, suggesting the location of the resistor isn't critical; but then you might see it is. In motherboards, the series resistors are often at the edge of the DDR connector, not as close to the driver as possible.

Having a series resistor at your input shouldn't affect your timing much (such as for bidir lines); at that point the only delay seen is the RC for the series resistor and the input parasitics. For example, 35 ohm and 8 pF gives a 280 ps time constant which is small for the overall timing budget in the slower DDR implementation.

The biggest suggestion I have is to keep the DDR-side stubs to a minimum, reducing the problems introduced by the impedance mismatch.

simulation.

trying to get them as short as possible, I haven't done yet the layout and it's just a worst case estimate.

looked awful !

undershoot and overshoot.

ohm seemed like a good value but it's more try & test than a real computed values ( track impedance is 70 ohm, at least that's what the simulation tool tells me ).

strenght. The Fast 16ma seems the best.

series resistor at each end ?

resistor is placed at the output of the output buffer but not at the input of the input buffer, so I suppose it's even better.

seen to recognize the output driver description in Micron's IBIS models, I still have to investigate this.

ok ? Any advice ?

quite cheap and I can't afford to have to redesign it multiples times, I'd like the first one to work ;)

Just in case you haven't already seen it, I would recommend taking a look at the Spartan-3 133 MHz DDR SDRAM reference design that supports up to DDR266 (PC2100) . Much of the engineering effort is already done.

The application note and reference design is on the Xilinx Memory Corner.

You'll want "XAPP768c: 133 MHz DDR Interface for Spartan-3 HDL Code". The application note and reference design are available to registered Xilinx web site viewers (which is a PITA, but unfortunately, that's the policy).

Another recommendation is to take a look at the following overview application note. This one is available without registering.

XAPP802: Memory Interface Application Notes Overview

Also, depending on the specific memory device you are using, you probably want to use one of the SSTL I/O standards. Likewise, some of the Micron devices, and probably others, have SSTL_2, Class II output buffers and offer a reduced drive strength option for low load or point-to-point designs.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

--------------------------------- Spartan-3: Make it Your ASIC

simulation.

trying to get them as short as possible, I haven't done yet the layout and it's just a worst case estimate.

looked awful !

undershoot and overshoot.

ohm seemed like a good value but it's more try & test than a real computed values ( track impedance is 70 ohm, at least that's what the simulation tool tells me ).

strenght. The Fast 16ma seems the best.

series resistor at each end ?

resistor is placed at the output of the output buffer but not at the input of the input buffer, so I suppose it's even better.

seen to recognize the output driver description in Micron's IBIS models, I still have to investigate this.

ok ? Any advice ?

quite cheap and I can't afford to have to redesign it multiples times, I'd like the first one to work ;)

Looking at the results that doesn't change much the appearence of the signals or the delay.

Yes, I'm planning on slow DDR (100Mhz), so that doesn't seem to have much impact.

Ok, given that the DDR chips are very close to the FPGA, the resitors might in fact be at the same distance from FPGA than the DDR chips.

Sylvain

I had a look at some application notes from Xilinx of course. But I didn't saw that one. I'm waiting for approbation from the "memory team". The ones I looked at had no mention of terminations, only considerations about trace lenght/delay. (Or I missed them). I just saw on a Virtex2 userguide and in SelectI/O app note that for SSTL_2 and DDR, they use a pull resistor of 50 ohm to Vtt=1.25v at both ends with a series of 25ohm. But that seem complicated, probably not needed for slow DDR and that will draw significantly more current than a simple series termination.

In a Micron app note, then they only use a 60 ohm series resitor at the middle of point to point connection.

Not much informations about signal integrity there.

Yes, they indeed uses SSTL_2 (Micron's chips)

Thanks for the suggestions,

Sylvain Munaut