DDR controller : problems about burst access

I recently tried out DDR controller design from Xilinx(xapp608), and found it does not work properly during simulation when I tried to use full burst read and write. I want to burst for one full row, but the controller always stops after it reaches column 508, I wonder why? Has anybody used this before?

Regards Hongtu

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virtex II pro ddr controller(xapp608)
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