Dear all,
I am working on a DDR controller that stores captured video frames from which a VGA controller retrieves data. It (DDR controller) works fine for the first few frames but seems dead afterward. I wonder if anyone experienced similar problem. What I did (for initial testing purpose) is to capture and store a frame into the DDR then retrieve the same frame (a 640x480 pixels area) over and over again.
Comments?
-M
I don't really know how DDR manages refreshing, have you taken care of it?
Zara
Hi Mike, I've got some experience with DDR2 controller. If you send me your code I can have a look.
Francesco
Zara,
Yes the controller is configured to auto-refresh DDR at the required intervals.
-M
Hi Francesco I am currently working on DDR2 controller for BL 8. My own code is giving good results when i verified with memory model from MICRON. Now my problem is memory on the board is not sending 4 DQS clock pulses. it seems to be sending for burst lenth 4.
For ur IDEA some results i observed
If i won't Initialize properly it is not responding at all . no DQS nothing is comming . if i initialize it properly its giving DQS signal of two sine clock pulses. If i write with 101010101 .... of each location i am getting two sine clock pulses on DQ pin while reading . if i write with all ZERO's i am getting ZERO' on DQ pin.
so i think inialization is happenig properly. some problem persistence still some where . If u have any IDEA please help me regarding this. with regards...... sudhakar
Hi sudhakar, What kind of FPGA wre you using? On the samsung website you can download some ddr2 memory model to verify that the initialization is ok. I don't have enought informations from you to help you. Last time I used MIG 7.1 succesfully . So if you are using a Xilinx FPGA I can reccomend you to use the MIG.
Francesco
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