HELP! How to constrain source-synchronous DDR inputs in Xilinx? In Synplify Pro?
Double Data Rate input scenario:
CLK = 500MHz (Period = 2ns, Pd/2=1ns, Pd/4=0.5ns)
Data rate = 1.0 Gb/sec (Ideal bit valid window = 1ns)
time t=0.0 1.0 2.0 3.0 4.0 etc... __________ __________ _______ CLK _________| |__________| |_________|
_____________________________________________________________ DATAi___X__________X__________X__________X__________X__________X__
_____________________________________________________________ DATAa___XXX_______XX__________XXX_______XX__________XXX_______XX__
DATAi = ideal (perfect edges, 0.5ns Tsu/Th before/after CLK edge) DATAa = actual (degraded edges, smaller valid window, less Tsu/Th)
Assume DATAa is valid 300ps before clock edge, 400ps after clock edge, for a total valid time of 700ps.
The clock does go into a DCM, and data is captured in DDR IOB flops
Assume no clock jitter either; I'm just trying to figure out the Xilinx UCF constraint syntax by example; their data books are inconsistent...
# With this: NET "CLK" TNM_NET = "CLK"; TIMESPEC "TS_CLK" = PERIOD "CLK" 2.0 ns HIGH 50.00%; NET "DATA" TNM = "DATA";
# I've tried this: TIMEGRP "DATA" OFFSET = IN: 0.3 : BEFORE CLK; TIMEGRP "DATA" OFFSET = IN: 0.4 : AFTER CLK;
# And this: TIMEGRP "DATA" OFFSET = IN: 0.3 VALID 0.7: BEFORE CLK HIGH; TIMEGRP "DATA" OFFSET = IN: 0.4 VALID 0.7: BEFORE CLK FALL;
And several other variants, but get nothing sensible (or nothing at all) out of the compiler and timing reports. Ditto for entering Synplicity scripts and asking it to pass good .ucf/ncf forward...
I'm much more accustomed to the Synopsys Design Constraints format (DesignCompiler/PrimeTime), and I'm struggling to get this thru Synplify and ISE.
Sorry if the post is premature. I didn't find much yet by googling, but wanted to get this out to the world before the weekend, since I'll since I'll be working most of it. 8-P
Thanks in advance for your help!
mj