DDC design

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Hi,

Can anyone point me at a vhdl design for a DDC, Digital Down Convertor,
in an FPGA. Preferably free.
It should be a wideband design with up to 10MHz and as low as 100KHz
bandwidth. Resolution of adc is 14bits.
Also it should be possible to synthesise it with the Xilinx Webpack.

Thanks for any help

Jan



Re: DDC design
There is a free DDC Xilinx core that comes with the ISE tools (not sure
about Webpack). It is not a VHDL design though...

/Mikhail



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Re: DDC design
It is pretty straight forward.  See my article in XCell about digital
downcoverters.  There is a link on the publications page of my website to
the paper.

Jan wrote:

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--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
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