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DCM LOCKED as reset

Hi, Can DCM's LOCKED o/p signal be used as reset within FPGA? is this scheme feasible :-

PowerON Reset acts as DCM reset. DCM's "Locked" signal, shifted by 1 SRL16 acts as reset for all the functionality (say FSMs) within FPGA.

*FSM has active low reset

The possible need for this scheme: When PowerON reset connected to DCM reset gets De-asserted, DCM starts "loking" the clock. At the same time, if same PowerON reset is used as reset, all the FFs in the functionality are reseted.

but while DCM is not "LOCKED", there are some clock pulses at the output of DCM, which might be of variable "period". So, just to avoid any "false trgiggering" of FSMs with these clock pulses, "locked" signal will keep the FSM in "reset state". when "Locked" signal goes high still it is delayed by 16clocks (1 SRL16). So when this reset gets removed, all the functionality will be receiving "stable" DCM clock.

Cheers Manish

Reply to
manishr
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Manish, There is a option in DCM to release FPGA done once the DCM stabilize. You can use this option also. Even i donot see any problem if LOCK is used as FPGA internal reset.

Have fun working, Thanks and Regards Praveen

Reply to
praveen

We use the LOCKED signal as async reset for our XC2V and XC3S designs. In case we have several cascaded DCMs, the 1st one rst the 2nd one, which in turn rst the 3rd one, till the last one which rst the complete design.

Eric

Reply to
Eric DELAGE

designs.

please, use sync resets a) statemachines releasing this reset, you can't ensure that all FFs become active with the same clock-edge - so a one-hot-sm may not be one-hot anymore b) ressources using sync resets will save ressources, because synthesis can use reset-port of a FF to implement sync. logic

you're not (under 'normal' circumstances) allowed to cascade 3 DCMs, because 2nd DCM's output-jitter will exceed 3rd's input-jitter-requirement

Jochen

Reply to
Jochen

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