Hi all,
I have a design which takes data from an external ADC. The ADC provides a 35 Mhz clock.
Currently the design feeds the input clock through a DCM and uses the
180 degree phase shifted version to sample and reassemble the ADC data. This all then passes to our system clock domain via one of the (wonderfully useful) Xilinx self addressing asychronous FIFO's.As this is for a communications system we need to perform clock recovery (actually this might be better described as carrier recovery) and the ADC provides a means to tune the clock it uses to sample with. Of course this means that the clock we are feeding into the DCM to get our internal sampling clock (and driving the SAF - in essense a block RAM) is going to be changing. Each change could be in the order of 200 Hz and performed a few thousand times a second. The total change from the clock the DCM locked with could be up to 100 KHz but I could bodge...ahem...design my way round this to make it significantly less.
Although the above is working fine at the moment I am worried about the DCM loosing its lock due to the varying input clock. Can anyone suggest how much the DCM will tolerate before throwing a wobbly?
Thanks,
Andy