DCM for generating higher frequencies.

Hi all, Given a clock of 20Mhz can I generate 320Mhz clock output using single DCM in Xilinx FPGA?

Regards Raghavendra.Sortur.

Reply to
Raghavendra
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Raghavendra,

Yes.

M=16, D=1 will multiply the 20 MHz on CLKIN to 320 MHZ on CLKFX output.

The clock GUI assumes that you are also using the DLL feature at the same time (ie CLKFB is connected) and it applies the minimum input clock frequency for that feature. If you are using the synthesizer only, the input frequency is not limited (except by the resulting output frequency as a choice of M and D).

Aust> Hi all,

Reply to
Austin Lesea

More:

Looks like the data sheet has a spec of 50 MHz as the min for the CLKIN for the DFS in high frequency mode.

Not sure how that got in there....

Researching that now. M=16 with Fin = 20 MHz does get you to 320 MHz output.

It may also be that the jitter is not so great with large M's and small input clock frequencies (greater than 10% of the period), so I have to get the jitter calculator to also let me enter 20 MHz in HF mode to see what it tells me.

Aust> Raghavendra,

Reply to
Austin Lesea

Further,

Baased on the jitter predictor:

Fin = 20 MHz, Fout = 320 MHz, M=16, D = 1

Output period = ~ 3.12 Period jitter = 700 ps p-p (worst case) Period Jitter = 22.2%

Not a very good quality clock, as you have to deal with the worst case jitter divided by two taking away from your timing margin (worst case shortest possible period).

Aust> More:

Reply to
Austin Lesea

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