I just generated a design with XPS, using edk 6.3i. It had a DDR controller, and a bus speed 4x lower than the 100Mhz CPU.
The problem is, when I try to simulate this design, nothing happens, since the second DCM in the chain does not generate ANY output signals. I cannot find any cause of this. I didn't modify any of the settings, I just generated and then went straigt to simulation in modelsim.
The chain is as follows:
DCM1 : clk divider, from 100 to 25 mhz DCM2 : clk shifter, generates shifted signals