Hello, I have an input clock of 125MHz coming to VirtexII device. I want to derive 80MHz clock from it. The way I wanted to go is to use CLKFX output with 16/25 (M/D) factor. Can I do this without violating timing requirements for the DCM? Both the input and output frequencies are within allowed range and I get no warnings neither from architecture wizard nor from online CLKFX jitter calculator, however I'm not fully understand the sentence from user guide ug002:
"For example, assume input frequency = 50 MHz, M = 25, and D = 8 (note that M and D values have no common factors and hence cannot be reduced). The output frequency is correctly 156.25 MHz, although 25 x 50 MHz =
1.25 GHz and 50 MHz / 8 = 6.25 MHz, and both of these values are far outside the range of the input frequency."Does this mean that I cannot use 16/25 factor in my case?