hi
I have another question about DCM's: If I use the design wizard to generate a vhdl file for a DCM the wizard uses all kinds of Buffers. For example it also uses a "BUFG" in the feedback loop. CLK0 -> BUFG -> CLKFB. Is that necessary? Do I have to use an IBUFG for the CLKIN of a DCM if nothing else is connected to that CLK signal? I still a beginner in vhdl so please bear with me. Thanks for all the help urban