DC component removal in FPGA

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Hello,
I am designing a system using Virtex 4 FPGA. The FPGA is interfaced
with a 12-bit A/D. The problem is that the A/D generates an inherent dc
component in the digital values it ships to the FPGA. This is impacting
my results at the lower end of my specs.
The methods I have thought of are
1. Trim the A/D manually using a resistor
2. pass the lower 3-bits of the A/D word through a large moving average
filter at the input(filter design is a pain!!)
Is there any other method which can be used
Thanks
MORPHEUS


Re: DC component removal in FPGA
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Check out Ken Chapmans TechExclusives at www.xilinx.com
there its explained how todo this

antti
http://gforge.openchip.org



Re: DC component removal in FPGA
Hey Antti,
Thanks a ton, the paper was too helpful. This kind of a design will
improve my system performance by alot.
Thanks
MORPHEUS


Re: DC component removal in FPGA

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:)  thanks, I hoped it would be!
It makes always sense to read very carfully all the stuff Ken Chapman
writes! Tons of stuff to learn. I actually used that technique in 'digital
carrier frequency amplifier' for SG bridge and LVDT sensors. It was using
XC2S200E and microblaze and some digital path and simple filter etc..

Antti



Re: DC component removal in FPGA
Hey Antti,
I was wondering if this circuit works well with 2's complement data
also 'coz I implemented it and it doesnt seem to work. For 2's
complement data, the subtractor at the begining of the ckt needs to be
an adder...right?
Thanks
MORPHEUS


Re: DC component removal in FPGA

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If you can afford run a calibrate cycle at start-up, you can subtract
the DC using a simple adder in the FPGA.  Finding the value to subtract
(and adjusting it as the DC offset drifts) is the hard part.   You can
use a CIC filter with a fairly high decimation ratio to extract the DC
value with relatively little complexity.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
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Re: DC component removal in FPGA

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Exponentially smooth the incoming samples to get the average value,
and subtract that from the data stream.

Kohn


Re: DC component removal in FPGA
Kohn,
Thanks for replying, could you elaborate a little more
Thanks
MORPHEUS


Re: DC component removal in FPGA

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Exponential smoothing just simulates an R-C lowpass filter.

Define a filter box, with samples S coming in and output F going out.
Now, every sample clock, do

    F = F + (S-F) / N

where N is the smoothing factor. If N is a power of two, the divide is
just a right-shift. So you can do this with just a register, two
adders, and a misaligned bus to do the shift.

F will settle to the mean value of S. Keep N pretty big to reduce the
small output ripple, or cascade two filter boxes. Making the filter
word size bigger than the ADC "S" word width helps a bit; in other
words, keep some or at least a few bits of the right-shifted stuff.

So just subtract F from each incoming sample. (S-F) is in there
somewhere already, so that's free.

In integer math, you'll have all the usual rounding and rollover and
sign extension issues to worry about. Still, it's not hard and works
well.

Done carefully, this will actually AC-couple the signal to an accuracy
of a fraction of an LSB.

John


 

Re: DC component removal in FPGA
Hey John,
Thanks, the suggestions are quite helpful
Thanks
MORPHEUS


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