I have configured an XCV1000 as a data and instruction cache. It is connected to a external hard core. I would like to be able to update the contents of the caches without recompiling the file. I have been using Data2mem, but it appears that the CRC bits for the bitstream are not recalculated. They are always set to: 0xDEFC
When data2mem modifies a bit file, it apparently turns off CRC checking by replacing the calculated CRC value with a constant 0xDEFC (which apparently spells DEFault Crc value). 0xDEFC is apparently supposed to tell the FPGA not to bother doing a CRC check on load because we were apparently TOO LAZY to calculate a correct value to check against.
I found one (non-xilinx) web site that indicated that Virtex-II etc. will work just fine without a valid CRC value, but not so for Virtex.
ngdbuild, or one of those tools near it, explicitly states that "-g CRC:DISABLE" is a valid command line option for Virtex-II but not Virtex, and indeed project navigator complains when I attempt "-g CRC:DISABLE" for our part.
It seems clear at the moment that data2mem is not calculating CRC values but is calculating a bypass value instead; and it's less clear, but all signs seem to indicate, that that would work for Virtex-II and later parts but won't work for Virtex.
I think there must be a way to get the CRC in the bitfile, hopefully using data2mem, but I haven't found it yet.
Has anyone run into this problem and solved it? Here is a diff of the two bit files.
Diff between working bitfile addr11.bit, generated by bitgen, and nonworking bitfile tmp.bit, generated by data2mem:
6c6 < Command: data2mem -bm tmp.bmm -bt addr11.bit -d