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Data2Mem usage - help required

THIS IS IN CONTINUATION TO THE THREAD I MADE A COUPLE OF DAYS AGO. I WANTED TO ISOLATE THIS FROM THE OTHER STUFF, HENCE THE NEW THREAD: Refer here for the older thread:

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Hi,

Here's what I need to do.

1) I will generate the data in a text file using Python scripts. 2) Will probably write another script or use Matlab to convert this to a .mem format which is readable by Xilinx. 3) Will use data2mem from command line to convert .mem file to either a .bit file or .v file. I will first try with verilog file, which I will then include into the project. The verilog file will contain the initialization for the RAM. Later on, I am planning to just use data2mem to generate .bit file, so that I can directly download it to the FPGA. (The different web-pages on Xilinx talk about .elf file, but as I don't have any code to write on the FPGA, but rather just some data, I don't know whether I should be concerned about this or not)

Now, if I understand it correctly, these are the only steps required. Is it necessary to do something about the RAM in the hardware design? Like specifying where to store, the memory design etc?

Update:

Ok, I tried to do this. I defined a simple mem file like this:

@0000 2A

3B 4C 5D

I saved this as example.mem.

Now, I tried data2mem -bd example.mem -o v outputverilog.v

I was expecting a verilog file at the output. However, nothing happens. There is no error, but no output file either.

Any help would be appreciated.

Thanks, Robert.

Reply to
Robert
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Hi Robert, you also need to write an BMM file. Otherwise data2mem has no idea of the memory segmentation inside your FPGA.

like this:

// 3 Blocks of 256 Addresses by 32 Bits of Data

ADDRESS_SPACE aemb_rom RAMB4 INDEX_ADDRESSING [0x000:0x5ff]

BUS_BLOCK XLXI_9/XLXI_1/BRAM/Mram_RAM_Modul_inst_ramb_1[31:16] LOC = R0C0 OUTPUT = ROM0_high.mem; XLXI_9/XLXI_1/BRAM/Mram_RAM_Modul_inst_ramb_0[15:0] LOC = R1C0 OUTPUT = ROM0_low.mem; END_BUS_BLOCK;

BUS_BLOCK XLXI_9/XLXI_2/BRAM/Mram_RAM_Modul_inst_ramb_1[31:16] LOC = R4C0 OUTPUT = ROM1_high.mem; XLXI_9/XLXI_2/BRAM/Mram_RAM_Modul_inst_ramb_0[15:0] LOC = R5C0 OUTPUT = ROM1_low.mem; END_BUS_BLOCK;

BUS_BLOCK XLXI_9/XLXI_3/BRAM/Mram_RAM_Modul_inst_ramb_1[31:16] LOC = R2C0 OUTPUT = ROM2_high.mem; XLXI_9/XLXI_3/BRAM/Mram_RAM_Modul_inst_ramb_0[15:0] LOC = R3C0 OUTPUT = ROM2_low.mem; END_BUS_BLOCK;

END_ADDRESS_BLOCK;

The LOC-infos come from the floorplaner UCF-output after PAR. The Path is adapted from the blockname (replace the appropriate underscores by slashes) and the bussegmentation, well, you simply got to know and add in the file.

The OUTPUT Statement gives the filename for each segments file.

I spent a lot of time to find out about this because XILINX provides no straightforward information about the BMM syntax.

Have a nice synthesis Eilert

Robert schrieb:

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Reply to
backhus

Thanks Eilert. It worked!! Hurray!

I am surprised why Xilinx does not have proper documentation for this tool. I mean, of course, the documentation for data2mem is pretty good in that it explains what it does and what are the options. However, there are no examples. I did find one example BMM file in a data2bram document. However, I would hope they improve the one on data2mem.

Thanks again.

Robert.

Reply to
Robert

data2mem -bm|bd infile.[bmm|elf|mem] [options]

This lead me to think that I should give EITHER a bmm or a mem file as input, as opposed to both which are required.

Reply to
Robert

On a sunny day (18 Oct 2005 05:47:00 -0700) it happened "Robert" wrote in :

Yes any documentation without examples is worthless irritating shit. That is why I started adding examples in the 'application -h' output these days.

Reply to
Jan Panteltje

Hi Robert, sorry, I forgot to mention that. I fell into that very same trap when I did my first steps with data2mem. :-)

Have a nice synthesis Eilert

Robert schrieb:

Reply to
backhus

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