Hi,
Does anyone have a hint on how to get data2bram and coregen memory to work together?
I have an SoC with some 32bit memory made up of four 8bit memories generated with coregen, I've made a bmm file that defines the memory. I can run data2bram with the bmm file and an .elf file and if I set the output to verilog the init strings look resonable. If I run the same bmm and .elf file on my bit file and use the updated bit file to configure an FPGA DONE doesn't go high so I assume the bit file is corrupt.
Is there a trick I should know about ?
data2bram does give me a warning the the memory is not LOC'ed, is there a simple way to get that info when the memory is generated with coregen?
(xc2v3000 and ISE5.1)
-Lasse