I'm creating a dual-port ROM, both sides are the same: 7-bit address,
32-bit data. Very simple ISE 13.3 project can be downloaded from here:I'm aware of this page:
Am I doing something wrong here?
Testing on XC3S50A.
AFAIC, this is a bug and should be fixed. I'm creating a ROM, not a RAM.
I think this is probably OK. Have you simulated your design and/or seen that it works as you expect in hardware?
I have often seen similar warnings for unused address lines on block RAMs for Microblaze or PPC designs. The ROM and RAM are made from the same Block RAM primitives, so the same connection lines are there, even if not implemented.
Maybe somebody else will chime in with a more concrete answer though.
Steve
=BF
No, I haven't simulated it, it is too simple. (did you get the file?) And I haven't tested it with real hardware, bc that was just a test.
Maybe someone has 13.4 and has time to test it there? (synthesize and implement)
No. Open pins should generate a warning. Just tie them to '0'.
-- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------
OK.
But ISE should do that automatically, because there are other input pins in the BRAM that I'm not using, and ISE is not complaining about those pins.
Anyone knows how do I do that in specifically this project?
I've created a similar project, just replacing ROM with RAM.
it seems it has something to do with the WEA signal
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